NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 320

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8.1.13
Table 193. Offset 54h: TCO_CNTL—TCO Control (LPC I/F—D31:F0)
Intel
DS
320
Bits
Default Value:
7:4
2:0
3
®
6300ESB I/O Controller Hub
Lockable:
Device:
Offset:
TCO_INT_SEL: TCO
TCO_INT_EN: TCO
Interrupt Enable
Interrupt Select
Offset 54h: TCO_CNTL—TCO Control (LPC I/F—
D31:F0)
Reserved
31
54h
00h
No
Name
Reserved.
This bit enables/disables the TCO interrupt.
0 = Disables TCO interrupt.
1 = Enables TCO Interrupt, as selected by the TCO_INT_SEL
Specifies on which IRQ the TCO will internally appear. When
not using the APIC, the TCO interrupt must be routed to
IRQ9-11, and that interrupt is not shared with the SERIRQ
stream, but may be shared with other PCI interrupts. When
using the APIC, the TCO interrupt may also be mapped to
IRQ20-23, and may be shared with other interrupt. Note that
when the TCOSCI_EN bit is set (bit 6 of the GPEO_EN
register), the TCO interrupt will be sent to the same interrupt
as the SCI, and the TCO_INT_SEL bits will have no meaning.
When the TCO interrupt is mapped to APIC interrupts 9, 10 or
11, the signal is in fact active high. When the TCO interrupt is
mapped to IRQ 20, 21, 22, or 23 the signal is active low and
may be shared with PCI interrupts that may be mapped to
those same signals (IRQs).
Bits
000
001
010
011
100
101
110
111
field.
SCI Map
IRQ9
IRQ10
IRQ11
Reserved
IRQ20 (Only available when APIC enabled)
IRQ21 (Only available when APIC enabled)
IRQ22 (Only available when APIC enabled)
IRQ23 (Only available when APIC enabled)
Power Well:
Description
Attribute:
Function:
Size:
0
Read/Write
8-bit
Core
Order Number: 300641-004US
Intel
®
6300ESB ICH—8
November 2007
Access
R/W
R/W