NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 336

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 209. Offset E3h: FWH_DEC_EN1—FWH Decode Enable 1 Register (LPC I/F—
8.1.30
Table 210. Offset E4h - E5h: GEN1_DEC—LPC I/F Generic Decode Range 1 (LPC I/
Intel
DS
336
15:7
Bits
Bits
Default Value:
Default Value:
6:1
2
1
0
0
®
6300ESB I/O Controller Hub
Lockable:
Lockable:
Device:
Device:
GEN1_BASE: Generic I/
O Decode Range 1 Base
Offset:
Offset:
Decode Range 1 Enable
GEN1_EN: Generic
FWH_D0_EN
FWH_C8_EN
FWH_C0_EN
D31:F0) (Sheet 2 of 2)
Offset E4h - E5h: GEN1_DEC—LPC I/F Generic
Decode Range 1 (LPC I/F—D31:F0)
F—D31:F0)
Reserved
Address
31
E3h
FFh
No
Name
31
E4h - E5h
00h
Yes
Name
Enables decoding two 512 Kbyte FWH memory ranges.
0 = Disable.
1 = Enable the following ranges for the FWH
Enables decoding two 512 Kbyte FWH memory ranges.
0 = Disable.
1 = Enable the following ranges for the FWH
Enables decoding two 512 Kbyte FWH memory ranges.
0 = Disable.
1 = Enable the following ranges for the FWH
This address is aligned on a 128-byte boundary, and must
have address lines 31:16 as 0.
Note that this generic decode is for I/O addresses only, not
memory addresses. The size of this range is 128 bytes.
Reserved.
0 = Disable.
1 = Enable the GEN1 I/O range to be forwarded to the LPC I/
FFD00000h - FFD7FFFFh
FF900000h - FF97FFFFh
FFC80000h - FFCFFFFFh
FF880000h - FF8FFFFFh
FFC00000h - FFC7FFFFh
FF800000h - FF87FFFFh
F.
Power Well:
Power Well:
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
0
Read/Write
8-bit
Core
0
Read/Write
16-bit
Core
Order Number: 300641-004US
Intel
®
6300ESB ICH—8
November 2007
Access
Access
R/W
R/W
R/W
R/W
R/W