NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 612

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NHE6300ESB S L7XJ

Manufacturer Part Number
NHE6300ESB S L7XJ
Description
Manufacturer
Intel
Datasheet

Specifications of NHE6300ESB S L7XJ

Lead Free Status / RoHS Status
Compliant
Intel
DS
612
3
2
1
0
Offset:
Bits
Default Value:
®
Table 533. Timer n Config and Capabilities (Sheet 3 of 3)
6300ESB I/O Controller Hub
TIMERn_INT_TYPE_CNF
TIMERn_INT_ENB_CNF
TIMERn_TYPE_CNF
Reserved
Timer 0: 100-107h,
Timer 1: 120-127h,
Timer 2: 140-147h
N/A
Name
Timer n Type:
For Timers 1 and 2, this bit will always return ’0’ when read
and writes will have no impact.
For Timer 0, this bit is read/write, and may be used to enable
the timer to generate a periodic interrupt. Writing a 1 to this
bit enables the timer to generate a periodic interrupt.
NOTE: For timer 0, this bit will be read/write, with default of
Timer n Interrupt Enable: This bit must be set to enable timer
n to cause an interrupt when it times out. When this bit is ‘0’,
the timer may still count and generate appropriate status bits
but will not cause an interrupt. Default value is ‘0’.
Timer Interrupt Type:
0 = The timer interrupt is edge triggered. This means that an
1 = The timer interrupt is level triggered. This means that a
NOTE: The default value is ‘0’, edge-triggered. The interrupt
Reserved. These bits will return ’0’ when read.
edge-type interrupt is generated. When another interrupt
occurs, another edge will be generated.
level-triggered interrupt is generated. The interrupt will
be held active until it is cleared by writing to the bit in the
General Interrupt Status Register. When another
interrupt occurs before the interrupt is cleared, the
interrupt will remain active.
‘0’. For timers 1:2, this bit will be read-only, with a
fixed value of ‘0’.
type is not expected to be changed dynamically. The
interrupt type for any timer should be set before any
interrupts are generated by that timer. If the interrupt
type is changed dynamically, there will be some delay
before the new type takes effect. That delay is not
known at this time. Supports edge and level triggered
modes for all three timers.
Description
Attribute:
Size:
Read/Write
64-bit
Order Number: 300641-004US
Intel
®
6300ESB ICH—15
November 2007
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