NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 407

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8—Intel
Table 292. SMI_EN—SMI Control and Enable Register (Sheet 3 of 3)
8.8.3.10 SMI_STS—SMI Status Register
November 2007
Order Number: 300641-004US
Bits
Default Value:
I/O Address:
2
1
0
Lockable:
®
Note: When the corresponding _EN bit is set when the _STS bit is set, the Intel
Note: Usage: ACPI or Legacy.
Device:
6300ESB ICH
EOS: End of SMI
GBL_SMI_EN
ICH will cause an SMI# (except bits 8-10 and 12, which do not need enable bits since
they are logically ORed with other registers that have enable bits). The Intel
ICH uses the same GPE0_EN register (I/O address: PMBase+2Ch) to enable/disable
both SMI and ACPI SCI general purpose input events. ACPI OS assumes that it owns
the entire GPE0_EN register per ACPI spec. Problems arise when some of the general-
purpose inputs are enabled as SMI by BIOS, and some of the general purpose inputs
are enabled for SCI. In this case ACPI OS turns off the enabled bit for any GPIx input
signals that are not indicated as SCI general-purpose events at boot, and exit from
sleeping states. BIOS should define a dummy control method which prevents the ACPI
OS from clearing the SMI GPE0_EN bits.
BIOS_EN
31
PMBASE + 30h
00000000h
No
Name
0 = Disable.
1 = Enables the generation of SMI# when ACPI software
This bit controls the arbitration of the SMI signal to the
processor. This bit must be set for the Intel
assert SMI# low to the processor.
0 = Once the Intel
1 = When this bit is set, SMI# signal will be deasserted for 4
NOTE: The Intel
0 = No SMI# will be generated by the Intel
1 = Enables the generation of SMI# in the system upon any
writes a 1 to the GBL_RLS bit.
bit is automatically cleared.
PCI clocks before its assertion. In the SMI handler, the
processor should clear all pending SMIs (by servicing
them and then clearing their respective status bits), set
the EOS bit, and exit SMM. This will allow the SMI arbiter
to re-assert SMI upon detection of an SMI event and the
setting of a SMI status bit.
This bit is reset by a PCI reset event.
enabled SMI event.
after reset even though EOS bit is not set. Subsequent
SMI require EOS bit is set.
®
®
6300ESB ICH is able to generate 1st SMI
6300ESB ICH asserts SMI# low, the EOS
Power Well:
Description
Attribute:
Function:
Size:
0
Read/Write
32-bit
Core
®
®
6300ESB ICH to
6300ESB ICH.
Intel
®
6300ESB I/O Controller Hub
®
®
6300ESB
(special)
Access
6300ESB
R/W
R/W
R/W
407
DS