NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 633

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

17—Intel
Table 559. Offset 04 - 05h: APIC1CMD—APIC1 COMMAND Register (APIC1—
17.1.3
Table 560. Offset 06 - 07h: APIC1STA—APIC1 Device Status (APIC1—D29:F5)
November 2007
Order Number: 300641-004US
15:1
10:9
Bits
Bits
Default Value:
Default Value:
5:3
8:6
3:0
6
2
1
0
1
5
4
Lockable:
Lockable:
Device:
Device:
BME: Bus Master Enable
®
Offset:
Offset:
66MHZ_CAP: 66 MHz
MSE: Memory Space
DEV_STS: DEVSEL#
6300ESB ICH
PERE: Parity Error
Response Enable
Capabilities List
Timing Status
D29:F5) (Sheet 2 of 2)
Offset 06 - 07h: APIC1STA—APIC1 Device Status
(APIC1—D29:F5)
Reserved
Reserved
Reserved
Reserved
Reserved
capable
Enable
29
04-05h
0000h
No
Name
29
06 - 07h
0010h
No
Name
0 = No action is taken when detecting a parity error.
1 = The Intel
NOTE: D30FO offset F4h, bit #2 must be set to a ‘1’ AND
Reserved.
Controls the I/O APIC1’s ability to act as a master on Hub
Interface when forwarding processor side bus interrupt
messages.
Controls the I/O APIC1’s response as a target to memory
accesses that address the I/O APIC1.
Reserved.
Reserved.
00 = Fast Decode.
NOTE: These bits are set for fast decode ‘00’, but a true
Reserved.
Hardwired to 1. Not 66 MHz capable.
This bit is hardwired to ‘1’, indicating the presence of a valid
capabilities pointer at offset 34h.
Reserved.
parity error is detected.
D28FO offset F4h, bit #2 must be set to a ‘1’ in order
for PERE to have any effect.
device select does not exist, so they have no effect.
®
6300ESB ICH will take normal action when a
Power Well:
Power Well:
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
5
Read/Write
16-bit
Core
5
Read-Only
16-bit
Core
Intel
®
6300ESB I/O Controller Hub
Access
Access
R/W
R/W
R/W
RO
RO
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