NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 118

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5.6.4.5
5.6.4.6
5.6.4.7
5.6.4.8
Intel
DS
118
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6300ESB I/O Controller Hub
In this mode, internal status is updated by software control during OCW2. However, it
is independent of the EOI command. Priority changes may be executed during an EOI
command by using the Rotate on Specific EOI Command in OCW2 (R=1, SL=1, EOI=1
and LO-L2=IRQ level to receive bottom priority.
Poll Mode
Poll mode may be used to conserve space in the interrupt vector table. Multiple
interrupts that may be serviced by one interrupt service routine do not need separate
vectors when the service routine uses the poll command. Poll mode may also be used
to expand the number of interrupts. The polling interrupt service routine may call the
appropriate service routine, instead of providing the interrupt vectors in the vector
table. In this mode, the INTR output is not used and the microprocessor internal
Interrupt Enable flip-flop is reset, disabling its interrupt input. Service to devices is
achieved by software using a Poll command.
The Poll command is issued by setting P=1 in OCW3. The PIC treats its next I/O read as
an interrupt acknowledge, sets the appropriate ISR bit when there is a request, and
reads the priority level. Interrupts are frozen from the OCW3 write to the I/O read. The
byte returned during the I/O read will contain a ‘1’ in bit 7 when there is an interrupt,
and the binary code of the highest priority level in bits 2:0.
Cascade Mode
The PIC in the Intel
onto the master through IRQ2. This configuration may handle up to 15 separate
priority levels. The master controls the slaves through a three bit internal bus. In the
Intel
takes responsibility for returning the interrupt vector. An EOI command must be issued
twice: once for the master and once for the slave.
Edge and Level Triggered Mode
In ISA systems this mode is programmed using bit 3 in ICW1, which sets level or edge
for the entire controller. In the Intel
register for edge and level triggered mode selection, per interrupt input, is included.
This is the Edge/Level control Registers ELCR1 and ELCR2.
When an ELCR bit is ‘0’, an interrupt request will be recognized by a low to high
transition on the corresponding IRQ input. The IRQ input may remain high without
generating another interrupt. When an ELCR bit is ‘1’, an interrupt request will be
recognized by a high level on the corresponding IRQ input and there is no need for an
edge detection. The interrupt request must be removed before the EOI command is
issued to prevent a second interrupt from occurring.
In both the edge and level triggered modes, the IRQ inputs must remain active until
after the falling edge of the first internal INTA#. When the IRQ input goes inactive
before this time, a default IRQ7 vector will be returned.
End of Interrupt Operations
An EOI may occur in one of two fashions: by a command word write issued to the PIC
before returning from a service routine, the EOI command; or automatically when AEOI
bit in ICW4 is set to one.
®
6300ESB ICH, when the master drives 010b on this bus, the slave controller
®
6300ESB ICH has one master 8259 and one slave 8259 cascaded
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6300ESB ICH, this bit is disabled and a new
Order Number: 300641-004US
Intel
®
6300ESB ICH—5
November 2007