NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 25

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Contents—Intel
17
18
November 2007
Order Number: 300641-004US
APIC1 Configuration Registers
(D29:F5)631
17.1
17.2
PCI-X Overview (D28:F0) ...................................................................................... 647
18.1
18.2
18.3
18.4
18.5
18.6
16.5.3 Reload Sequence.................................................................................. 630
16.5.4 Low Power State .................................................................................. 630
APIC1 Configuration Registers (D29:F5) ............................................................. 631
17.1.1 Offset 00 - 03h: VID_DID—Vendor/ID Register
17.1.2 Offset 04 - 05h: APIC1CMD—APIC1 COMMAND Register (APIC1—D29:F5) ... 632
17.1.3 Offset 06 - 07h: APIC1STA—APIC1 Device Status
17.1.4 Offset 08h: RID—Revision ID Register (APIC1—D29:F5) ............................ 634
17.1.5 Offset 09 - 0Bh: CC—Class Code Register (APIC1—D29:F5) ....................... 634
17.1.6 Offset 0C - 0Fh: HEADTYP—Header Type Register
17.1.7 Offset 2C - 2Fh: SS—APIC1 Subsystem Identifiers
17.1.8 Offset 34h: CAP_PTR—APIC1 Capabilities Pointer
17.1.9 Offset 3Ch: ILINE—Interrupt Line (APIC1—D29:F5) .................................. 636
17.1.10 Offset 3Dh: IPIN—Interrupt Pin (APIC1—D29:F5) ..................................... 636
17.1.11 Offset 40 - 41h: ABAR—APIC1 Alternate Base Address Register (APIC1—D29:F5)
17.1.12 Offset 44 - 47h: MBAR—APIC1 Memory Base Register (APIC1—D29:F5) ...... 637
17.1.13 Offset 50 - 51h: XID—PCI-X Identifiers Register
17.1.14 Offset 52h: XSR—PCI-X Status Register (APIC1—D29:F5) ......................... 639
Advanced Interrupt Controller (APIC) ................................................................. 640
17.2.1 APIC1 Direct Register Map ..................................................................... 640
17.2.2 IND—Index Register ............................................................................. 640
17.2.3 DAT—Data Register .............................................................................. 641
17.2.4 IRQPA—IRQ Pin Assertion Register ......................................................... 641
17.2.5 EOIR—EOI Register .............................................................................. 642
17.2.6 Offset 00h: ID—Identification Register .................................................... 643
17.2.7 Offset 01h: VER—Version Register .......................................................... 643
17.2.8 Offset 03h: BOOT_CONFIG—Boot Configuration Register ........................... 644
17.2.9 Redirection Table ................................................................................. 644
I/O Window Addressing .................................................................................... 647
Memory Window Addressing ............................................................................. 648
18.2.1 Memory Base and Limit Address Registers ............................................... 648
18.2.2 Prefetchable Memory Base and Limit Address Registers, Upper 32-Bit Registers ..
VGA Addressing .............................................................................................. 649
Configuration Addressing.................................................................................. 650
18.4.1 Type 0 Accesses to the Intel
18.4.2 Type 1 to Type 0 Translation.................................................................. 650
18.4.3 Type 1 to Type 1 Forwarding ................................................................. 651
18.4.4 Type 1 to Special Cycle Forwarding......................................................... 651
Transaction Ordering ....................................................................................... 652
18.5.1 Comparison of Rules vs. a PCI – PCI Bridge ............................................. 652
18.5.2 Other Notes......................................................................................... 652
Device 28 – Hub Interface to PCI-X Bridge.......................................................... 653
18.6.1 Configuration Space Registers ................................................................ 653
®
6300ESB ICH
(APIC1—D29:F5).................................................................................. 632
(APIC1—D29:F5).................................................................................. 633
(APIC1—D29:F5).................................................................................. 635
(APIC1—D29:F5).................................................................................. 635
(APIC1—D29:F5).................................................................................. 636
637
(APIC1—D29:F5).................................................................................. 639
648
18.6.1.1 Register Summary .................................................................. 653
®
6300ESB ICH ............................................ 650
Intel
®
6300ESB I/O Controller Hub
DS
25