NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 64

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

3.5
Table 7.
3.6
Table 8.
Intel
DS
64
®
6300ESB I/O Controller Hub
SATA Interface
SATA Interface Signals
IDE Interface
IDE Interface Signals (Sheet 1 of 2)
NOTES:
1. The IDE signals are 5V tolerant.
2. The IDE signals have integrated series terminating resistors.
3. All signals may be tri-stated or driven low for mobile swap bays.
SATARBIASN
SATARBIASP
PDD[15:0],
SATACLKP,
SATA0RXN
SATA1RXN
SDD[15:0]
SATA0TXN
SATA0RXP
SATA1TXN
SATA1RXP
SATACLKN
SATALED#
SATA0TXP
SATA1TXP
PDA[2:0],
SDA[2:0]
PDDREQ,
PDCS1#,
PDCS3#,
SDDREQ
SDCS1#
SDCS3#
Name
Name
Type
Type
I/O
OD
O
O
O
O
O
I
I
I
I
i
Primary and Secondary IDE Device Chip Selects for 100 Range:
For ATA command register block. This output signal is connected to
the corresponding signal on the primary or secondary IDE connector.
Primary and Secondary IDE Device Chip Select for 300 Range:
For ATA control register block. This output signal is connected to the
corresponding signal on the primary or secondary IDE connector.
Primary and Secondary IDE Device Address: These output
signals are connected to the corresponding signals on the primary or
secondary IDE connectors. They are used to indicate which byte in
either the ATA command block or control block is being addressed.
Primary and Secondary IDE Device Data: These signals directly
drive the corresponding signals on the primary or secondary IDE
connector. There is a weak internal pull-down resistor on PDD[7] and
SDD[7].
Primary and Secondary IDE Device DMA Request: These input
signals are directly driven from the DRQ signals on the primary or
secondary IDE connector. It is asserted by the IDE device to request a
data transfer, and used in conjunction with the PCI bus master IDE
function and are not associated with any AT compatible DMA channel.
There is a weak internal pull-down resistor on these signals.
Serial ATA 0 Differential Transmit Pair: Outbound high speed
differential signals to Port 0.
Serial ATA 0 Differential Receive Pair: Inbound high speed
differential signals from Port 0.
Serial ATA 1 Differential Transmit Pair: Outbound high speed
differential signals to Port 1.
Serial ATA 1 Differential Receive Pair: Inbound high speed
differential signals from Port 1.
Differential SATA Clock: 100 MHz clock input from the Clock
Generator
Serial ATA LED#: Output indicates Serial ATA Drive activity when it
is driven low
Serial ATA Resistor Bias: Analog connection point for a external
resistor to ground.
Description
Description
Order Number: 300641-004US
Intel
®
6300ESB ICH—3
November 2007