NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 27

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Contents—Intel
19
November 2007
Order Number: 300641-004US
18.9
18.10 Delayed/Split Transactions ............................................................................... 698
18.11 Internal Bus/Device Communication .................................................................. 700
18.12 Data Return Behavior of Hub Interface Initiated Reads ......................................... 701
18.13 Performance Targets........................................................................................ 701
Serial I/O Unit....................................................................................................... 703
19.1
19.2
19.3
19.4
19.5
18.8.2 Attributes ............................................................................................ 691
18.8.3 Special Notes for Burst Transactions ....................................................... 692
18.8.4 Device Select Timing ............................................................................ 692
18.8.5 Wait States ......................................................................................... 692
18.8.6 Split Transactions ................................................................................. 693
18.8.7 Transaction Termination as a PCI-X Target .............................................. 694
18.8.8 Arbitration........................................................................................... 694
18.8.9 Bridge Buffer Requirements ................................................................... 694
18.8.10 Locked Transactions ............................................................................. 694
18.8.11 Error Support ...................................................................................... 695
Transaction Termination Translation between Interfaces ....................................... 695
18.9.1 Behavior of Hub Interface Initiated Cycles to PCI/PCI-X
18.9.2 Behavior of Hub Interface Initiated Cycles to PCI-X Receiving Split Terminations.
18.9.3 Hub Interface Action on Immediate Responses to PCI-X Split Completions ... 697
18.9.4 Behavior of PCI/PCI-X Initiated Cycles to Hub Interface ............................. 698
18.10.1 Number Supported ............................................................................... 698
18.10.2 Prefetch Algorithm................................................................................ 699
18.10.3 Algorithm (Multiple PCI-X Devices Requesting) ......................................... 700
18.10.4 Accesses From Multiple Agents to Same 4K Page ...................................... 700
18.13.1 Introduction ........................................................................................ 701
18.13.2 Definitions and Assumptions .................................................................. 701
18.13.3 Active Master Clock Counts .................................................................... 702
Features ........................................................................................................ 703
Pin Description................................................................................................ 704
19.2.1 Universal Asynchronous Receive And Transmit (UART0, UART1) ................. 704
Functional Description...................................................................................... 706
19.3.1 Host Processor Interface (LPC) ............................................................... 706
LPC Interface .................................................................................................. 706
19.4.1 LPC Cycles .......................................................................................... 706
19.4.2 Reset Policy ......................................................................................... 707
19.4.3 LPC Transfers ...................................................................................... 707
Logical Device 4 and 5: Serial Ports (UARTs) ....................................................... 707
19.5.1 Overview ............................................................................................ 707
®
6300ESB ICH
18.8.6.1 Completer Attributes ............................................................... 693
18.8.6.2 Requirements for Accepting Split Completions ............................ 693
18.8.6.3 Split Completion Messages ....................................................... 693
18.8.6.4 Arbitration Among Multiple Split Completions.............................. 693
18.8.7.1 Retry .................................................................................... 694
18.8.7.2 Split Response........................................................................ 694
18.8.7.3 Master-Abort .......................................................................... 694
18.8.11.1General ................................................................................. 695
18.8.11.2Special Parity Error Rule for Split Response ................................ 695
Receiving Immediate Terminations ......................................................... 695
696
18.10.2.1Parameters ............................................................................ 699
18.10.2.2Algorithm (Single Device Only) ................................................. 699
19.4.1.1 I/O Read and Write Cycles ....................................................... 706
19.4.3.1 I/O Transfers ......................................................................... 707
19.5.1.1 UART Feature List ................................................................... 708
19.5.1.2 UART Operational Description ................................................... 709
Intel
®
6300ESB I/O Controller Hub
DS
27