NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 714

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 643. Interrupt Identification Register Decode
19.5.1.3.5 FIFO Control Register (FCR)
Table 644. FIFO Control Register (FCR) (Sheet 1 of 2)
Intel
DS
714
®
6300ESB I/O Controller Hub
Note: The use of bit 6 and 7 is different from the register definition of standard 16550.
FCR is a write only register that is located at the same address as the IIR (IIR is a read
only register). FCR enables/disables the transmitter/receiver FIFOs, clears the
transmitter/receiver FIFOs, and sets the receiver FIFO trigger level.
3 2 1 0
0 0 0 1 -
0 1 1 0
0 1 0 0
1 1 0 0
0 0 1 0
0 0 0 0
FIFO Control Register
FCR
write-only
Interrupt
Number
ID bits
7:6
Bit
Interrupt SET/RESET Function
Highes
t
Secon
d
Highes
t
Secon
d
Highes
t
Third
Highes
t
Fourth
Highes
t
Priority
Bit Mnemonic
ITL[1:0]
None
Receiver
Line Status
Received
Data
Available.
Character
Timeout
indication.
Transmit
FIFO Data
Request
Modem
Status
Type
Address:
Reset State:
Access:
Interrupt Trigger Level: When the number of bytes in the
receiver FIFO equals the interrupt trigger level programmed into
this field and the Received Data Available Interrupt is enabled
(through IER), an interrupt is generated and appropriate bits are
set in the IIR.
00 = 1 byte or more in FIFO causes interrupt (same as 16550).
01 = RSVD
10 = 8 bytes or more in FIFO causes interrupt and DMA request
(same as 16550).
11 = RSVD
No Interrupt is pending.
Overrun Error, Parity Error,
Framing Error, Break Interrupt.
Non-FIFO mode: Receive
Buffer is full.
FIFO mode: Trigger level
was reached.
FIFO Mode only: At least one
character is in receiver FIFO
and there was no activity for a
time period.
Non-FIFO mode: Transmit
Holding Register Empty
FIFO mode: Transmit FIFO
has half or less than half
data.
Clear to Send, Data Set
Ready, Ring Indicator,
Received Line Signal Detect
Source
Base + 02H
00H
8-bit
Function
-
Reading the Line Status Register.
Non-FIFO mode: Reading the
Receiver Buffer Register.
FIFO mode: Reading bytes until
Receiver FIFO drops below trigger
level or setting RESETRF bit in FCR
register.
Reading the Receiver FIFO or
setting RESETRF bit in FCR register.
Reading the IIR Register (if the
source of the interrupt) or writing into
the Transmit Holding Register.
Reading the IIR Register (if the
source of the interrupt) or writing to
the Transmitter FIFO.
Reading the modem status
register
Order Number: 300641-004US
RESET Control
Intel
®
6300ESB ICH—19
November 2007