NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 300

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NHE6300ESB S L7XJ

Manufacturer Part Number
NHE6300ESB S L7XJ
Description
Manufacturer
Intel
Datasheet

Specifications of NHE6300ESB S L7XJ

Lead Free Status / RoHS Status
Compliant
7.1.22
Table 168. Offset 32 - 33h: IOLIM_HI—I/O Limit Upper 16 Bits Register (HUB-
7.1.23
Table 169. Offset 3Ch: INT_LINE—Interrupt Line Register (HUB-PCI—D30:F0)
Intel
DS
300
15:0
Bits
Bits
Default Value:
Default Value:
7:0
®
6300ESB I/O Controller Hub
Device:
Device:
I/O Address Limit Upper
Offset:
Offset:
Interrupt Line Routing
16 bits [31:16]
Offset 32 - 33h: IOLIM_HI—I/O Limit Upper 16
Bits Register
(HUB-PCI—D30:F0)
PCI—D30:F0)
Offset 3Ch: INT_LINE—Interrupt Line Register
(HUB-PCI—D30:F0)
30
32-33h
0000h
Name
30
3Ch
00h
Name
Hardwired to 00h. The bridge does not generate interrupts,
and interrupts from downstream devices are routed around
the bridge.
Not supported; hardwired to 0.
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
0
Read-Only
16-bit
0
Read-Only
8-bit
Order Number: 300641-004US
Intel
®
6300ESB ICH—7
November 2007
Access
Access
RO
RO

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