NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 385

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8—Intel
8.8.1.1
Table 272. Offset A0h: GEN_PMCON_1—General PM Configuration 1 Register
November 2007
Order Number: 300641-004US
15:1
Bits
Default Value:
8:6
3:2
1:0
10
1
9
5
4
Lockable:
®
Note: Usage: ACPI or Legacy.
Device:
Offset:
CPUSLP_EN: CPU SLP#
PER_SMI_SEL: Periodic
6300ESB ICH
SMI# rate Select
PWRBTN_LVL
SMI_LOCK
Offset A0h: GEN_PMCON_1—General PM Configuration 1
Register
(PM—D31:F0)
(PM—D31:F0)
Reserved
Reserved
Reserved
Reserved
Enable
31
A0h
00h
No
Name
Reserved.
Reserved.
This read-only bit indicates the current state of the PWRBTN#
signal.
0 = Low.
1 = High.
Reserved.
0 = Disable.
1 = Enables the CPUSLP# signal to go active in the S1-D
Note that CPUSLP# will go active on entry to S3, S4 and S5
even when this bit is not set.
When this bit is set, writes to the GLB_SMI_EN bit will have
no effect Once the SMI_LOCK bit is set, writes of 0 to
SMI_LOCK bit will have no effect (i.e. once set, this bit may
only be cleared by PXPCIRST#).
Reserved.
Set by software to control the rate at which periodic SMI# is
generated.
00 = 64 seconds
01 = 32 seconds
10 = 16 seconds
11 = 8 seconds
states. This reduces the processor power.
Power Well:
Description
Attribute:
Function:
Size:
0
Read/Write
16-bit
Core
Intel
®
6300ESB I/O Controller Hub
Access
R/WO
R/W
R/W
RO
385
DS