NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 38

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Intel
DS
38
271
272 Offset A0h: GEN_PMCON_1—General PM Configuration 1 Register (PM—D31:F0) ............ 385
273 Offset A2h: GEN_PMCON_2—General PM Configuration 2 Register (PM—D31:F0) ............ 386
274 Offset A4h: GEN_PMCON_3—General PM Configuration 3 Register (PM—D31:F0) ............ 387
275 Offset ACh: RST_CNT2—Reset Control 2 Register (PM—D31:F0) ................................... 388
276 Offset B8h - BBh: GPI_ROUT—GPI Routing Control Register (PM—D31:F0)..................... 389
277 Offset C0h: MON_FWD_EN—IO Monitor Forward Enable Register (PM—D31:F0) .............. 390
278 Offset C4h, C6h, C8h, CAh: MON[n]_TRP_RNG—I/O Monitor [4:7] Trap Range
279 Offset CCh: MON_TRP_MSK—I/O Monitor Trap Range Mask Register for Devices 4-7 (PM—
280 APM Register Map ................................................................................................... 392
281 APM_CNT—Advanced Power Management Control Port Register .................................... 392
282
283 ACPI and Legacy I/O Register Map ............................................................................ 393
284 PM1_STS—Power Management 1 Status Register ........................................................ 394
285 PM1_EN—Power Management 1 Enable Register ......................................................... 396
286 PM1_CNT—Power Management 1 Control ................................................................... 397
287 PM1_TMR—Power Management 1 Timer Register ........................................................ 398
288 PROC_CNT—Processor Control Register ..................................................................... 398
289 LV2—Level 2 Register ............................................................................................. 400
290 GPE0_STS—General Purpose Event 0 Status Register .................................................. 401
291 GPE0_EN—General Purpose Event 0 Enables Register .................................................. 404
292 SMI_EN—SMI Control and Enable Register ................................................................. 405
293 SMI_STS—SMI Status Register................................................................................. 408
294 ALT_GP_SMI_EN—Alternate GPI SMI Enable Register .................................................. 410
295 ALT_GP_SMI_STS—Alternate GPI SMI Status Register ................................................. 411
296 MON_SMI—Device Monitor SMI Status and Enable Register .......................................... 411
297 DEVACT_STS—Device Activity Status Register ............................................................ 412
298 DEVTRAP_EN— Device Trap Enable Register .............................................................. 414
299 BUS_ADDR_TRACK— Bus Address Tracker ................................................................. 415
300 BUS_CYC_TRACK— Bus Cycle Tracker ....................................................................... 416
301 TCO I/O Register Map ............................................................................................. 416
302 TCO1_RLD—TCO Timer Reload and Current Value ....................................................... 417
303 TCO1_TMR—TCO Timer Initial Value ......................................................................... 417
304 TCO1_DAT_IN—TCO Data In Register ....................................................................... 418
305 TCO1_DAT_OUT—TCO Data Out Register................................................................... 418
306 TCO1_STS—TCO1 Status Register ............................................................................ 419
307 TCO2_STS—TCO2 Status Register ............................................................................ 421
308 TCO1_CNT—TCO1 Control Register ........................................................................... 422
309 TCO2_CNT—TCO2 Control Register ........................................................................... 423
310 TCO_MESSAGE1 and TCO_MESSAGE2 Registers ......................................................... 423
311 Offset TCOBASE + OEh: TCO_WDSTATUS—TCO2 Control Register ................................ 424
312 Offset TCOBASE + 10h: SW_IRQ_GEN—Software IRQ Generation Register..................... 424
313 Registers to Control GPIO ........................................................................................ 425
314 Offset GPIOBASE + 00h: GPIO_USE_SEL—GPIO Use Select Register ............................. 426
315 Offset GPIOBASE + 04h: GP_IO_SEL—GPIO Input/Output Select Register...................... 426
316 Offset GPIOBASE + 0Ch: GP_LVL—GPIO Level for Input or Output Register.................... 427
317 Offset GPIOBASE + 18h: GPO_BLINK—GPO Blink Enable Register ................................. 429
318 Offset GPIOBASE + 2Ch: GPI_INV—GPIO Signal Invert Register ................................... 430
319 Offset GPIOBASE + 30h:GPIO_USE_SEL2—GPIO Use Select 2 Register.......................... 431
320 Offset GPIOBASE + 34h: GP_IO_SEL2—GPIO Input/Output Select 2 Register ................. 432
321 Offset GPIOBASE + 38h: GP_LVL2—GPIO Level for Input or Output 2 Register ............... 432
322 PCI Configuration Map (IDE-D31:F1)......................................................................... 435
323 Offset 00 - 01h: VID—Vendor ID Register (LPC I/F—D31:F1) ....................................... 436
®
6300ESB I/O Controller Hub
Power Management PCI Configuration Registers
Register for Devices 4-7 (PM—D31:F0)...................................................................... 391
D31:F0)391
APM_STS—Advanced Power Management Status Port Register
(D31:F0)............................................ 384
..................................... 392
Intel
Order Number: 300641-004US
®
6300ESB ICH—Contents
November 2007