NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 624
NHE6300ESB S L7XJ
Manufacturer Part Number
NHE6300ESB S L7XJ
Description
Manufacturer
Intel
Datasheet
1.NHE6300ESB_S_L7XJ.pdf
(848 pages)
Specifications of NHE6300ESB S L7XJ
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Table 548. Offset 2Dh - 2Ch: SVID—Subsystem Vendor ID
16.4.14 Offset 2Eh - 2Fh: SID—Subsystem ID
Table 549. Offset 2Eh - 2Fh: SID—Subsystem ID
Intel
DS
624
31:4
15:0
Bits
Bits
Default Value:
Default Value:
2:1
3
0
®
6300ESB I/O Controller Hub
Lockable:
Lockable:
Note: Software (BIOS) will write the value to this register. After that, the value may be read,
Device:
Device:
Offset:
Offset:
RTE - Resource Type
Base Address
Subsystem ID
Prefetchable
but writes to the register will have no effect. The write to this register should be
combined with the write to the SVID to create one 32-bit write.
Indicator
29
2Dh - 2Ch
00h
No
Name
29
2Eh-2Fh
00h
No
Name
Type
These bits are used to determine the size of the memory-
mapped region being requested.
Hard-wired to ‘0’, indicating that this range is not pre-
fetchable.
Hard-wired to ‘00’, indicating that this range can be mapped
anywhere in 32-bit address space.
Hard-wired to ‘0’, indicating a request for memory space.
Power Well:
Power Well:
Description
Attribute:
Attribute:
Description
Function:
Function:
Size:
Size:
4
Read, Write Once
16-bit
Core
4
Read, Write Once
16-bit
Core
Order Number: 300641-004US
Intel
®
6300ESB ICH—16
November 2007
Access
Access
R/W
RO
RO
RO
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