NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 253

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
Table 132. Slave Write Registers
Table 133. Command Types (Sheet 1 of 2)
.
November 2007
Order Number: 300641-004US
®
6300ESB ICH
NOTE: The external microcontroller is responsible to make sure that it does not update the
Command
Register
Type
9-FFh
1–3
6–7
0
1
2
3
4
5
6
0
4
5
8
contents of the data byte registers until they have been read by the system processor.
The Intel
condition is possible where the new value is being written to the register just at the time
it is being read. Intel
unpredictable results in this case).
Reserved
Wake/SMI#: Wake system if it is not already awake. If system is already
awake, then an SMI# will be generated.
NOTE: The SMB_WAK_STS bit will be set by this command, even when the
Unconditional Powerdown: This command sets the PWRBTNOR_STS bit, and
has the same effect as the Powerbutton Override occurring.
Hard Reset Without Cycling: The will cause a hard reset of the system (does
not include cycling of the power supply). This is equivalent to a write to the CF9h
register with bits 2:1 set to 1, but bit 3 set to 0.
Hard Reset System: The will cause a hard reset of the system (including
cycling of the power supply). This is equivalent to a write to the CF9h register
with bits 3:1 set to 1.
Disable the TCO Messages. This command will disable the Intel
ICH from sending Heartbeat and Event messages (as described in
Section 5.12.4, “Heartbeat and Event Reporting through
this command has been executed, Heartbeat and Event message reporting may
only be re enabled by assertion and deassertion of the RSMRST# signal.
WD Reload: Reload watchdog timer.
®
Command Register. See
Reserved
Data Message Byte 0
Data Message Byte 1
Reserved
Frequency Straps will be written on bits 3:0. Bits 7:4 should be 0, but will be
ignored.
Reserved
6300ESB ICH will overwrite the old value with any new value received. A race
system is already awake. The SMI handler should then clear this bit.
®
6300ESB ICH will not attempt to cover this race condition (i.e.
Table 133
Description
Function
for legal values written to this register.
Intel
®
6300ESB I/O Controller Hub
SMLink/SMbus”). Once
®
6300ESB
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