NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 302

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 170. Offset 3E - 3Fh: BRIDGE_CNT—Bridge Control Register (HUB-PCI—
Intel
DS
302
Bits
Default Value:
6
5
®
6300ESB I/O Controller Hub
Device:
Offset:
Secondary Bus Reset
Master Abort Mode
VGA 16-Bit Decode
D30:F0)
(Sheet 2 of 3)
30
3E-3Fh
0000h
Name
Controls PXPCIRST# assertion on PCI(X).
1 = The Intel
0 = The Intel
This bit controls the behavior of the Intel
when a master abort occurs on a transaction that crosses the
Hub Interface-PCI bridge in either direction. The default is 0.
When set to 0, the Intel
following manner:
When set to 1, the Intel
abort as an error:
This bit does not have any functionality relative to address
decodes because the Intel
cycles to PCI, independent of the decode. Writes of one have
no impact other than to force the bit to one. Writes of zero
have no impact other than to force the bit to zero. Reads to
this bit will return the previously written value (or zero when
no writes since reset).
• Hub Interface Completion-Required requests to PCI:
• Hub Interface Posted Writes to PCI: When these master
• PCI Reads to Hub Interface: When these master abort on
• PCI writes to Hub Interface: Intel
• Hub Interface Completion-Required requests to PCI:
• Hub Interface Posted Writes to PCI: When these master
• PCI Reads to Hub Interface: When these master abort on
• PCI writes to Hub Interface: The Intel
When these master abort on PCI, the Intel
returns a master abort status. For reads, FFFFh is
returned for each DWORD.
abort on PCI, the Intel
Hub Interface, the Intel
provided with the Hub Interface master abort packet to
the PCI requestor.
idea when these “master-abort.”
When these master abort on PCI, the Intel
returns a target abort status. For reads, FFFFh is returned
for each DWORD.
abort on PCI, the Intel
and sets the Primary Signaled SERR# bit (when the
corresponding SERR_EN bit is set).
Hub Interface, the Intel
cycle with a target abort and flushes the remainder of the
prefetched data.
no idea when these “master-abort.”
PCIXSBRST# is asserted, the data buffers between the
Hub Interface and PCI(X) and the PCI(X) bus are
initialized back to reset conditions. The Hub Interface and
the configuration registers are not affected.
®
®
6300ESB ICH asserts PCIXSBRST#. When
6300ESB ICH deasserts PCIXSBRST#
®
®
Description
Attribute:
Function:
6300ESB ICH behaves in the
®
6300ESB ICH treats the master
®
®
®
®
6300ESB ICH will forward the
6300ESB ICH discards the data.
6300ESB ICH discards the data
6300ESB ICH returns the data
6300ESB ICH terminates the
Size:
®
0
Read/Write
16-bit
6300ESB ICH has no
®
®
6300ESB ICH
6300ESB ICH has
®
®
6300ESB ICH
6300ESB ICH
Order Number: 300641-004US
Intel
®
6300ESB ICH—7
November 2007
Access
R/W
R/W