NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 56

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 3.
3.2
Table 4.
Intel
DS
56
®
6300ESB I/O Controller Hub
Hub Interface Signals
Firmware Hub Interface
Firmware Hub Interface Signals
NOTES:
NOTE: All LPC/FWH signals are in the core well.
HI_VSWING
1. The Hub Interface signals are all in a separate power plane, called the Hub Interface plane.
2. During the S3, S4, and S5 states, power to the Hub Interface is assumed to be off. During S0
FWH[3:0] /
FWH[4] /
LAD[3:0]
LFRAME#
and S1 states, power to the Hub Interface must be on.
HIREF
Name
Type
I/O
I/O
I
I
Hub Interface Voltage Reference. Analog input, expected
voltage 350mV
Hub Interface Voltage Swing: Analog input used to control the
voltage swing and impedance strength of Hub Interface pins.
Expected voltage is 800 mV.
NOTES:
Firmware Hub Signals. Muxed with LPC address signals. Internal
pull-ups are provided.
Firmware Hub Signals. Muxed with LPC LFRAME# signal. LFRAME#:
Indicates the start of an LPC cycle, or an abort.
1. Refer to the platform design guide for expected voltages.
2. Refer to the platform design guide for resistor values and routing
guidelines for each Hub Interface mode.
Description
Order Number: 300641-004US
Intel
®
6300ESB ICH—3
November 2007