NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 309
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NHE6300ESB S L7XJ
Manufacturer Part Number
NHE6300ESB S L7XJ
Description
Manufacturer
Intel
Datasheet
1.NHE6300ESB_S_L7XJ.pdf
(848 pages)
Specifications of NHE6300ESB S L7XJ
Lead Free Status / RoHS Status
Compliant
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7—Intel
7.1.30
Table 176. Offset 82h: PCI_MAST_STS—PCI Master Status Register (HUB-PCI—
7.1.31
Table 177. Offset 90h: ERR_CMD—Error Command Register (HUB-PCI—D30:F0)
November 2007
Order Number: 300641-004US
Bits
Bits
Default Value:
Default Value:
6:4
3:0
7:3
1:0
7
2
Lockable:
®
Note: This register configures the Intel
Device:
Status (PCI_MREQ_STS)
Device:
Offset:
Offset:
6300ESB ICH
Receiving Target Abort
Master Request Status
PCI Master Request
Internal South PCI
(INT_MREQ_STS)
SERR# Enable on
(SERR_RTA_EN)
Offset 82h: PCI_MAST_STS—PCI Master Status
Register (HUB-PCI—D30:F0)
D30:F0)
Offset 90h: ERR_CMD—Error Command Register
(HUB-PCI—D30:F0)
system errors. The actual assertion of the internal SERR# (routed to cause NMI# or
SMI#) is enabled through the PCI Command register.
Reserved
Reserved
Reserved
30
82h
00h
Name
30
90h
00h
No
Name
Allows software to see if the internal DMA controller or LPC
has requested use of the PCI bus.
0 = Software clears this bit by writing a’1‘to the bit position.
1 = The Intel
Reserved.
Allows software to see if a particular bus master has
requested use of the PCI bus.
0 = Software clears these bits by writing a 1 to the bit
1 = The associated PCI master has requested use of the PCI
Reserved.
0 = Disable.
1 = Enable. When SERR_EN is set, the Intel
Reserved. Bit 1 was the SERR# Enabled for Delayed
Transaction Timeout, see
BRIDGE_CNT—Bridge Control Register
has requested use of the PCI bus.
position.
bus.
will report SERR# when SERR_RTA is set.
®
6300ESB ICH’s internal DMA controller or LPC
®
6300ESB ICH’s Device 30 responses to various
Power Well:
Description
Description
Section 7.1.24, “Offset 3E - 3Fh:
Attribute:
Attribute:
Function:
Function:
Size:
Size:
0
Read/Write Clear
8-bit
0
Read/Write
8-bit
Core
(HUB-PCI—D30:F0)”.
®
6300ESB ICH
Intel
®
6300ESB I/O Controller Hub
Access
Access
R/WC
R/WC
R/W
309
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