NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 61

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

3—Intel
Table 6.
November 2007
Order Number: 300641-004US
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6300ESB ICH
PCI-X Interface Signals (Sheet 2 of 4)
PXFRAME#
PXTRDY#
PXIRDY#
PXSTOP#
PXPAR
Name
Type
I/O
I/O
I/O
I/O
I/O
Cycle Frame: The current Initiator drives PXFRAME# to indicate the
beginning and duration of a PCI transaction. While the initiator
asserts PXFRAME#, data transfers continue. When the initiator
negates PXFRAME#, the transaction is in the final data
phase.PXFRAME# is an input to the Intel
Intel
the Intel
Initiator. PXFRAME# remains tri-stated by the Intel
until driven by an Initiator.
Initiator Ready: PXIRDY# indicates the Intel
ability, as an Initiator, to complete the current data phase of the
transaction. It is used in conjunction with PXTRDY#. A data phase is
completed on any clock both PXIRDY# and PXTRDY# are sampled
asserted. During a write, PXIRDY# indicates the Intel
has valid data present on PXAD[31:0]. During a read, it indicates the
Intel
the Intel
and an output from the Intel
6300ESB ICH is an Initiator. PXIRDY# remains tri-stated by the
Intel
Target Ready: PXTRDY# indicates the Intel
as a Target to complete the current data phase of the transaction
PXTRDY# is used in conjunction with IRDY#. A data phase is
completed when both PXTRDY# and PXIRDY# are sampled asserted.
During a read, PXTRDY# indicates that the Intel
Target, has placed valid data on PXAD[31:0]. During a write,
PXTRDY# indicates the Intel
to latch data PXTRDY# is an input to the Intel
the Intel
6300ESB ICH when the Intel
tri-stated from the leading edge of PXPCIRST#. PXTRDY# remains
tri-stated by the Intel
Stop: PXSTOP# indicates that the Intel
is requesting the Initiator to stop the current transaction. PXSTOP#
causes the Intel
transaction. PXSTOP# is an output when the Intel
Target and an input when the Intel
PXSTOP# is tri-stated from the leading edge of PXPCIRST#.
PXSTOP# remains tri-stated until driven by the Intel
Calculated/Checked Parity: PXPAR uses “even” parity calculated
on 36 bits, PXAD[31:0] plus PXC/BE[3:0]#. “Even” parity means that
the Intel
plus PXPAR and the sum is always even. The Intel
always calculates PXPAR on 36 bits regardless of the valid byte
enables. The Intel
data phases and only ensures PXPAR to be valid one PCI clock after
the corresponding address or data phase. The Intel
drives and tri-states PXPAR identically to the PXAD[31:0] lines except
that the Intel
PXPAR is an output during the address phase (delayed one clock) for
all Intel
during the data phase (delayed one clock) when the Intel
ICH is the Initiator of a PCI-X write transaction, and when it is the
Target of a read transaction. The Intel
when it is the Target of a PC-X write transaction. When a parity error
is detected, the Intel
status bits, and has the option to generate an NMI# or SMI#.
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6300ESB ICH is the target, and PXFRAME# is an output from
6300ESB ICH is prepared to latch data. PXIRDY# is an input to
6300ESB ICH until driven by an Initiator.
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6300ESB ICH initiated transactions. PXPAR is an output
6300ESB ICH is the Initiator and an output from the Intel
6300ESB ICH counts the number of “1”s within the 36 bits
6300ESB ICH when the Intel
6300ESB ICH when the Intel
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6300ESB ICH delays PAR by exactly one PXPCI clock.
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6300ESB ICH, as an Initiator, to stop the current
6300ESB ICH generates PXPAR for address and
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6300ESB ICH will set the appropriate internal
6300ESB ICH until driven by a target.
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Description
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6300ESB ICH, as a Target is prepared
6300ESB ICH when the Intel
6300ESB ICH is a Target. PXTRDY# is
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6300ESB ICH is an Initiator.
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Intel
6300ESB ICH checks parity
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6300ESB ICH is the
6300ESB ICH is the Target
6300ESB ICH, as a Target,
6300ESB ICH when the
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6300ESB I/O Controller Hub
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6300ESB ICH's ability
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6300ESB ICH when
6300ESB ICH's
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6300ESB ICH, as a
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6300ESB ICH is a
6300ESB ICH
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®
6300ESB ICH
6300ESB ICH
6300ESB ICH.
6300ESB ICH
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6300ESB
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DS
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