NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 437

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

9—Intel
9.1.3
November 2007
Order Number: 300641-004US
15:1
Bits
Default Value:
10
1
9
8
7
6
5
4
3
2
1
0
Table 325. Offset 04h - 05h: CMD—Command Register (IDE—D31:F1)
®
Fast Back to Back Enable
Device:
IOSE - I/O Space Enable
Offset:
Postable Memory Write
6300ESB ICH
Memory Space Enable
Interrupt Disable (ID)
Parity Error Response
Special Cycle Enable
VGA Palette Snoop
Wait Cycle Control
Bus Master Enable
Enable (PMWE)
SERR# Enable
Offset 04h - 05h: CMD—Command Register (IDE—
D31:F1)
Reserved
(IOSE)
31
04h-05h
00h
Name
(BME)
(MSE)
(FBE)
(SCE)
Reserved.
Enables the P-ATA host controller to assert the INTA# (in
native mode) or IRQ14/15 (in legacy mode). When set, the
interrupt will be deasserted. When cleared, the interrupt may
be asserted.
Reserved as ‘0’.
Reserved as ‘0’.
Reserved as ‘0’.
Reserved as ‘0’.
Reserved as ‘0’.
Reserved as ‘0’.
Reserved as ‘0’.
Controls the Intel
master for IDE Bus Master transfers.
0 = Disables access.
1 = Enables access to the IDE Expansion memory range. The
NOTE: BIOS should set this bit to a 1.
This bit controls access to the I/O space registers.
0 = Disables access to the Legacy or Native IDE ports (both
1 = Enable. The Base Address register for the Bus Master
NOTES:
1. Separate bits are provided (IDE Decode Enable, in the IDE
2. When this bit is 0 and the IDE controller is in Native Mode,
Timing register) to independently disable the Primary or
Secondary I/O spaces.
the Interrupt Pin Register will be masked (the interrupt will
not be asserted) See
USB_RELNUM—USB Release Number Register (USB—
D29:F0/F1)”
Pin Register. When an interrupt occurs while the masking
is in place and the interrupt is still active when the
masking ends, the interrupt will be allowed to be asserted.
EXBAR register (Offset 24h) must be programmed before
this bit is set.
Primary and Secondary) as well as the Bus Master IO
registers.
registers should be programmed before this bit is set.
for more information regarding the Interrupt
®
6300ESB ICH’s ability to act as a PCI
Description
Section 10.1.16, “Offset 60h:
Attribute:
Function:
Size:
1
Read-Only, Read/Write
16-bit
Intel
®
6300ESB I/O Controller Hub
Access
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
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