NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 516

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 416. Offset CAPLENGTH + 10 - 13h: CTRLDSSEGMENT—Control Data
11.2.2.6 Offset CAPLENGTH + 14 - 17h: PERIODICLISTBASE—
Table 417. Offset CAPLENGTH + 14 - 17h: PERIODICLISTBASE—Periodic Frame
11.2.2.7 Offset CAPLENGTH + 18 - 1Bh: ASYNCLISTADDR—Current
Intel
DS
516
31:0
31:1
11:0
Bits
Bits
Default Value:
Default Value:
2
®
6300ESB I/O Controller Hub
Note: This 32-bit register contains the beginning address of the Periodic Frame List in the
Note: This 32-bit register contains the address of the next asynchronous queue head to be
Device:
Device:
Offset:
Offset:
Upper Address[63:32]
Base Address (Low)
Structure Segment Register
Periodic Frame
List Base Address
system memory. Since the Intel
(as indicated by the ‘1’ in the 64-bit Addressing Capability field in the HCCSPARAMS
register), then the most significant 32 bits of every control data structure address
comes from the CTRLDSSEGMENT register. HCD loads this register prior to starting the
schedule execution by the Host Controller. The memory structure referenced by this
physical memory pointer is assumed to be 4-Kbyte aligned. The contents of this
register are combined with the Frame Index Register (FRINDEX) to enable the Host
Controller to step through the Periodic Frame List in sequence.
List Base Address
Asynchronous List Address
executed. Since the Intel
indicated by a ‘1’ in 64-bit Addressing Capability field in the HCCPARAMS register), then
the most significant 32 bits of every control data structure address comes from the
CTRLDSSEGMENT register. Bits [4:0] of this register cannot be modified by system
software and will always return ‘0’s when read. The memory structure referenced by
this physical memory pointer is assumed to be 32-byte aligned.
Reserved
29
CAPLENGTH + 10-13h
00000000h
Name
29
CAPLENGTH + 14-17h
00000000h
Name
This 32-bit field corresponds to address bits 63:32 when
forming a control data structure address.
These bits correspond to memory address signals [31:12],
respectively.
Reserved. Must be written as ‘0’s. During runtime, the value
of these bits are undefined.
®
6300ESB ICH host controller operates in 64-bit mode (as
®
6300ESB ICH host controller operates in 64-bit mode
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
7
Read/Write
32-bit
7
Read/Write
32-bit
Order Number: 300641-004US
Intel
®
6300ESB ICH—11
November 2007
Access
Access
RW
RW