NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 438

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

9.1.4
Intel
DS
438
10:9
Bits
Default Value:
2:0
15
14
13
12
11
8
7
6
5
4
3
®
Table 326. Offset 06 - 07h: STS—Device Status Register (IDE—D31:F1)
6300ESB I/O Controller Hub
Device:
DEVSEL# Timing Status
User Definable Features
Offset:
Signaled System Error
Received Master-Abort
Capabilities List (CAP)
Signaled Target-Abort
Detected Parity Error
Interrupt Status (IS)
Fast Back-to-Back
Data Parity Error
66 MHz Capable
Status (RMA)
Status (STA)
Offset 06 - 07h: STS—Device Status Register
(IDE—D31:F1)
Reserved
Reserved
Detected
Capable
(DEVT)
31
06-07h
0280h
Name
(UDF)
(DPE)
(SSE)
Reserved as ‘0’.
Reserved as ‘0’.
0 Cleared by writing a 1 to it.
Bus Master IDE interface function, as a master, generated a
master-abort.
Reserved as ‘0’.
0 = Cleared by writing a 1 to it.
1 = The Intel
01 = Hardwired; however, the Intel
have a real DEVSEL# signal associated with the IDE unit, so
these bits have no effect.
Reserved as ‘0’.
Reserved as ‘1’.
Reserved as ‘0’.
Reserved as ‘0’.
Reserved as ‘0’
Reflects the state of interrupt at the input of the
enable.disable circuit. This bit is a 1 when the interrupt is
asserted.
1 = Interrupt is asserted.
0 = Interrupt has been cleared (independent of the state of
the Interrupt Disable bit in the command register.
Reserved as ‘0’.
targeted with a transaction that the Intel
terminates with a target abort.
®
6300ESB ICH IDE interface function is
Description
Attribute:
Function:
Size:
®
1
Read/Write Clear, Read-Only
16-bit
6300ESB ICH does not
®
6300ESB ICH
Order Number: 300641-004US
Intel
®
6300ESB ICH—9
November 2007
Access
R/WC
R/WC
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO