NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 502

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 405. Offset 70 - 73h: Intel Specific USB EHCI SMI (Sheet 2 of 2)
Intel
DS
502
15:1
11:1
Bits
Default Value:
9:6
19
18
17
16
2
0
5
4
3
2
1
0
®
6300ESB I/O Controller Hub
Device:
SMI on HCHalted Enable
Offset:
SMI on HCReset Enable
SMI on Periodic Enable
SMI on PMSCR Enable
SMI on Async Enable
SMI on PortOwner
SMI on CF Enable
SMI on HCHalted
SMI on HCReset
SMI on Periodic
SMI on CF
Reserved
Reserved
Enable
29
70-73h
00000000h
Name
This bit is set to ‘1’ whenever the Periodic Schedule Enable bit
transitions from ‘1’->’0’ or ‘0’->’1’
This bit is set to ‘1’ whenever the Configure Flag (CF)
transitions from ‘1’->’0’ or ‘0’->’1’.
This bit is set to ‘1’ whenever HCHalted transitions to ‘1’ as a
result of the Run/Stop bit being cleared.
This bit is set to ‘1’ whenever HCRESET transitions to ‘1’
Reserved. Hardwired to 00h.
Reserved.
When any of these bits are ‘1’ and the corresponding SMI on
PortOwner bits are ‘1’, the host controller will issue an SMI.
Unused ports should have their corresponding bits cleared.
When this bit is ‘1’ and SMI on PMSCR is ‘1’, the host
controller will issue an SMI.
When this bit is ‘1’ and SMI on Async is ‘1’, the host controller
will issue an SMI
When this bit is ‘1’ and SMI on Periodic is ‘1’, the host
controller will issue an SMI.
When this bit is ‘1’ and SMI on CF is ‘1’, then the host
controller will issue an SMI.
When this bit is a ‘1’ and SMI on HCHalted is ‘1’, the host
controller will issue an SMI.
When this bit is a ‘1’ and SMI on HCReset is ‘1’, host controller
will issue an SMI.
Power Well:
Description
Attribute:
Function:
Size:
7
Read/Write
32-bit
Suspend
Order Number: 300641-004US
Intel
®
6300ESB ICH—11
November 2007
Access
R/WC
R/WC
R/WC
R/WC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO