NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 102

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5.2.1.8
5.2.1.9
5.2.1.10 LPC Power Management
5.2.1.11 Configuration and Intel
Intel
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6300ESB I/O Controller Hub
Note: When the cycle is not claimed by any peripheral (and subsequently aborted), the Intel
Note: The Intel
Note: The Intel
I/O Cycles
For I/O cycles targeting registers specified in the Intel
the Intel
8-bit transfers. When the processor attempts a 16-bit or 32-bit transfer, the Intel
6300ESB ICH will break the cycle up into multiple 8-bit transfers to consecutive I/O
addresses.
6300ESB ICH will return a value of all ones (FFh) to the processor. This is to maintain
compatibility with ISA I/O cycles where pull-up resistors would keep the bus high when
no device responds.
Bus Master Cycles
The Intel
defined in the LPC specification. The Intel
thus supports two separate bus master devices. It uses the associated START fields for
Bus Master 0 (‘0010b’) or Bus Master 1 (‘0011b’).
Bus Masters should only perform memory read or memory write cycles.
LPCPD# Protocol
Same timings as for SUS_STAT#. Upon driving SUS_STAT# low, LPC peripherals will
drive LDRQ# low or tri-state it. The Intel
buffers. After driving SUS_STAT# active, the Intel
and tri-states (or drive low) LAD[3:0].
The Intel
is always asserted after LPCPD#”. The exception is the S1-M state. In that case,
LPCPD# (SUSSTAT#) will go active, but LRESET# (PXPCIRST#) will not go active.
LPC I/F Decoders
In order to allow the I/O cycles and memory mapped cycles to go to the LPC I/F, the
Intel
6300ESB ICH must be programmed with the same decode ranges as the peripheral.
The decoders are programmed through the Device 31:Function 0 configuration space.
devices with similar characteristics (specifically those with a “Retry Read” feature which
is enabled) to an LPC device when there is an outstanding LPC read cycle towards the
same PCI device or bridge. These cycles are not part of normal system operation, but
may be encountered as part of platform validation testing using custom test fixtures.
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6300ESB ICH includes several decoders. During configuration, the Intel
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6300ESB ICH performs I/O cycles as defined in the LPC spec. These will be
6300ESB ICH supports Bus Master cycles and requests (using LDRQ#) as
6300ESB ICH does not support LPC Bus Masters performing I/O cycles. LPC
6300ESB ICH does not follow one part of the LPC spec that says “LRESET#
6300ESB ICH cannot accept PCI write cycles from PCI-to-PCI bridges or
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6300ESB ICH Implications
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6300ESB ICH will shut off the LDRQ# input
6300ESB ICH has two LDRQ# inputs, and
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6300ESB ICH drives LFRAME# low,
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6300ESB ICH’s decode ranges,
Order Number: 300641-004US
Intel
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6300ESB ICH—5
November 2007
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