NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 233

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
5.18.11.1Overview
5.18.11.2Theory of Operation
Table 114. USB Debug Port Behavior (Sheet 1 of 2)
November 2007
Order Number: 300641-004US
®
6300ESB ICH
The Debug port facilitates OS and device driver debug. It allows the software to
communicate with an external console using a USB EHCI connection. Since the
interface to this link does not go through the normal USB EHCI stack, it allows
communication with the external console during cases where the OS is not loaded, the
USB EHCI software is broken, or where the USB EHCI software is being debugged.
Specific features of this implementation of a debug port are:
There are two operational modes for the USB debug port:
Detail for the registers mentioned in the next sections can be found in
“USB 2.0-Based Debug Port Register”
Registers”.
Behavioral Rules:
Table 114
registers as well as bits in the associated Port Status and Control register.
1. Mode 1 is when the USB port is in a disabled state from the viewpoint of a standard
2. Mode 2 is when the host controller is running (i.e., Host controller’s Run/Stop# bit
1. In both modes 1 and 2, the Debug Port controller must check for software
2. When the debug port is enabled by the debug driver, and the standard host
3. When the standard host controller driver suspends the USB port, then USB debug
4. The ENABLED_CNT bit in the debug register space is independent of the similar
•
•
•
•
OWNER_CN
Only works with an external USB 2.0 debug device (console)
Implemented for a specific port on the host controller
Operational anytime the port is not suspended AND the host controller is in D0
power state.
Capability is interrupted when port is driving USB RESET
host controller driver. In Mode 1, the Debug Port controller is required to generate a
“keepalive” packets less than 2 ms apart to keep the attached debug device from
suspending. The keepalive packet should be a standalone 32-bit SYNC field.
is 1). In Mode 2, the normal transmission of SOF packets will keep the debug
device from suspending.
requested debug transactions at least every 125 microseconds.
controller driver resets the USB port, USB debug transactions are held off for the
duration of the reset and until after the first SOF is sent.
transactions are held off for the duration of the suspend/resume sequence and until
after the first SOF is sent.
port control bit in the associated Port Status and Control register.
T
0
1
1
describes the debug port behavior related to the state of bits in the debug
ENABLED_C
NT
X
0
1
Enable
Port
X
X
0
and in
Run /
Stop
X
X
0
Section 11.2, “Memory-Mapped I/O
Suspen
d
X
X
X
Debug port is not being used.
Normal operation.
Debug port is not being used.
Normal operation.
Debug port in Mode 1. SYNC
keep alives sent plus debug
traffic.
Intel
Debug Port Behavior
®
6300ESB I/O Controller Hub
Section 11.2.3,
233
DS