NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 592
NHE6300ESB S L7XJ
Manufacturer Part Number
NHE6300ESB S L7XJ
Description
Manufacturer
Intel
Datasheet
1.NHE6300ESB_S_L7XJ.pdf
(848 pages)
Specifications of NHE6300ESB S L7XJ
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Intel
DS
592
Bits
Default Value:
7:2
1:0
8
®
Table 515. Offset 54h: PCS—Power Management Control and Status Register
6300ESB I/O Controller Hub
Lockable:
Device:
Offset:
Event Enable (PMEE)
Power Management
Power State (PS)
(Modem—D31:F6) (Sheet 2 of 2)
Reserved
29
54h
0000h
No
Name
When set, and if corresponding PMES is also set, the AC'97
controller sets the AC97_STS bit in the GPE0_STS register.
Reserved.
This field is used both to determine the current power state of
the AC’97 controller and to set a new power state. The values
are:
00 – D0 state
01 – not supported
10 – not supported
11 – D3
When in the D3
space is available, but the I/O and memory spaces are not.
Additionally, interrupts are blocked.
When software attempts to write a value of 10b or 01b to this
field, the write operation must complete normally. However,
the data is discarded and no state change occurs.
HOT
state
HOT
state, the AC’97 controller’s configuration
Power Well:
Description
Attribute:
Function:
Size:
5
Read/Write
16-bit
Resume
Order Number: 300641-004US
Intel
®
6300ESB ICH—14
November 2007
Access
R/W
R/W
RO
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