NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 249

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
5.19.2.2 I
5.19.2.3 Heartbeat for Use with the External LAN Controller
5.19.3
5.19.4
5.19.4.1 Clock Stretching
November 2007
Order Number: 300641-004US
®
Note: When operating in I
Note: The Intel
6300ESB ICH
When the I
communicate with I
In addition, the Intel
independent of the I
block commands.
The Heartbeat method allows the Intel
LAN Controller when the processor is otherwise unable to do so. It uses the SMLINK I/F
between the Intel
message is a Block Write. Only eight bytes are sent.
Bus Arbitration
Several masters may attempt to get on the bus at the same time by driving the
SMBDATA line low to signal a start condition. The Intel
continuously monitor the SMBDATA line. When the Intel
to drive the bus to a ‘1’ by letting go of the SMBDATA line, and it samples SMBDATA
low, then some other master is driving the bus and the Intel
transferring data.
When the Intel
collision. The Intel
and when enabled, generate an interrupt or SMI#. The processor is responsible for
restarting the transaction.
When the Intel
Intel
bytes as a master on writes, it will drive data relative to the clock it is also driving. It
will not start toggling the clock until the start or stop condition meets proper setup and
hold time. The Intel
transactions as a master.
the System Management (SMLINK) interfaces.
Bus Timing
Some devices may not be able to handle their clock toggling at the rate that the Intel
6300ESB ICH as an SMBus master would like. They have the capability of stretching
the low time of the clock. When the Intel
(allowing the clock to go high), the clock will remain low for an extended period of time.
1. The Process Call command will skip the Command code (and its associated
2. The Block Write command will skip sending the Byte Count (DATA0).
2
C Behavior
acknowledge).
®
6300ESB ICH is sending address or command as an SMBus master, or data
®
6300ESB ICH supports the same arbitration protocol for both the SMBus and
2
C_EN bit is set, the Intel
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®
6300ESB ICH sees that it has lost arbitration, the condition is called a
6300ESB ICH is a SMBus master, it will drive the clock. When the
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®
2
6300ESB ICH and the external LAN Controller. The actual Heartbeat
2
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2
6300ESB ICH will set the BUS_ERR bit in the Host Status Register,
C mode the Intel
®
C devices. This forces the following changes:
C_EN bit.
6300ESB ICH will also ensure minimum time between SMBus
6300ESB ICH will support the new I
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®
®
6300ESB ICH SMBus logic will instead be set to
6300ESB ICH will not use the 32-byte buffer for
6300ESB ICH to send messages to an external
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6300ESB ICH attempts to release the clock
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6300ESB ICH must
6300ESB ICH is attempting
2
C Read command. This is
Intel
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6300ESB ICH must stop
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6300ESB I/O Controller Hub
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DS