NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 152

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5.11.6
Table 68.
Intel
DS
152
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6300ESB I/O Controller Hub
Note: The Intel® 6300ESB ICH does support THRM# based throttling. The C1 state
Dynamic Processor Clock Control
The Intel
system clocks. The clock control is used for transitions among the various S0/Cx states,
and processor throttling. Each dynamic clock control method is described in this
section. The various Sleep states may also perform types of non-dynamic clock control.
The Intel
supported.
The Dynamic Processor Clock control is handled using the following signal:
(processor auto halt) may be used with either one or two processors, however.
Processors are free to perform their own dynamic clock control; however, this is done
without any coordination by the Intel® 6300ESB ICH.
The C1 state is entered based on the processor performing an auto halt instruction.
The C2 state is entered based on the processor reading the Level 2 register in the
Intel
A C1 or C2 state ends due to a break event. Based on the break event, the Intel
6300ESB ICH returns the system to C0 state.
from C2 states. The break events from C1 are indicated in the processor’s datasheet.
Break Events
The Intel
ing the FERR# signal. The following rules apply:
Any unmasked interrupt
goes active
Any internal event that will
cause an NMI or SMI#
Any internal event that will
cause INIT# to go active
Processor Pending break
event Indication
1. When STPCLK# is detected active by the processor, the FERR# signal from the
2. When the Intel
3. When the Intel
4. When the processor detects the deassertion of STPCLK#, the processor will start
•
STPCLK#: Used to halt processor instruction stream.
processor will be redefined to indicate whether an interrupt is pending. The signal is
active low (i.e., FERR# will be low to indicate a pending interrupt).
the FERR# signal and continue to present this state to the FERR# state machine
(independent of what the FERR# pin does after the latching).
the FERR# signal as a break event indication. When FERR# is sampled low, a break
event is indicated. This will force a transition to the C0 state.
driving the FERR# signal with the natural value (i.e.the value it would do when the
pin was not muxed). The time from STPCLK# inactive to the FERR# signal
transition back to the native function must be less than 120 ns.
®
6300ESB ICH.
®
®
®
6300ESB ICH supports the Pending Break Event (PBE) indication from the processor us-
Event
6300ESB ICH supports the ACPI C0, C1 and C2 states. C3 and C4 are not
6300ESB ICH has extensive control for dynamically starting and stopping
®
®
6300ESB ICH asserts STPCLK#, it will latch the current state of
6300ESB ICH detects the Stop-Grant cycle, it will start looking at
Breaks from
C2
C2
C2
C2
Many possible sources.
IRQ[0:15] when using the 8259s, IRQ[0:23] for
I/O xAPIC0 and I/O xA[IC1. Since SCI is an
interrupt, any SCI will also be a break event.
Could be indicated by the keyboard controller
through the RCIN input signal.
Only available when FERR# enabled for break
event indication (See FERR# Mux-En in
Section 8.1.22, “Offset D0h - D3h: GEN_CNTL—
General Control Register (LPC
Table 68
lists the possible break events
Comment
Order Number: 300641-004US
Intel
I/F—D31:F0)”).
®
6300ESB ICH—5
November 2007
®