NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 373

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8—Intel
8.5.9
Table 257. Offset 02h: ARBID—Arbitration ID Register
8.5.10
Table 258. Offset 10h - 11h (Vector 0) through 3E - 3Fh (Vector 23): Redirection
November 2007
Order Number: 300641-004US
31:1
63:5
55:4
47:1
Bits
Bits
Default Value:
Default Value:
0
6
8
7
®
Device:
Device:
Extended Destination ID
Offset:
Offset:
6300ESB ICH
DT: Delivery Type
Destination
Offset 03h: BOOT_CONFIG—Boot Configuration
Register
Offset 10h - 11h (Vector 0) through 3E - 3Fh
(Vector 23): Redirection Table
The Redirection Table has a dedicated entry for each interrupt input pin. The
information in the Redirection Table is used to translate the interrupt manifestation on
the corresponding interrupt pin into an APIC message.
The APIC will respond to an edge triggered interrupt as long as the interrupt is held
until after the acknowledge cycle has begun. Once the interrupt is detected, a delivery
status bit internally to the I/O APIC is set. The state machine will step ahead and wait
for an acknowledgment from the APIC bus unit that the interrupt message was sent
over the APIC bus. Only then will the I/O APIC be able to recognize a new edge on that
interrupt pin. That new edge will only result in a new invocation of the handler if its
acceptance by the destination APIC causes the Interrupt Request Register bit to go
from 0 to 1. (i.e., when the interrupt was not already pending at the destination).
See
Table
Reserved
Reserved
(Sheet 1 of 2)
(EDID)
31
02h
00000000h
Name
31
10h-11h (vector 0)
through
3E-3Fh (vector 23)
Bit 16-1, Bits[15:12]=0.
All other bits undefined
Name
Table 259
for Delivery Mode Encoding information.
Reserved
Hardwire to 1. Interrupt delivery mechanism is always a
Processor System Bus message.
When bit 11 of this entry is 0 [Physical], then bits [59:56]
specify an APIC ID. In this case, bits 63:59 should be
programmed by software to 0.
When bit 11 of this entry is 1 [Logical], bits [63:56] specify
the logical destination address of a set of processors.
These bits are only sent to a local APIC when in Processor
System Bus mode. They become bits [11:4] of the address.
Reserved. Software should program these bits to 0
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
0
Read-Only
32-bit
0
Read/Write
64-bit (accessed as two 32 bit
quantities)
Intel
®
6300ESB I/O Controller Hub
Access
Access
R/W
RO
373
DS