NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 628

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

16.4.19 Offset Base + 04h: Preload Value 2 Register
Table 554. Offset Base + 04h: Preload Value 2 Register
Prel oad Valu e 2 Regi ster
16.4.20 Offset Base + 08h: General Interrupt Status
Table 555. Offset Base + 08h: General Interrupt Status Register
Prel oad Valu e 2 Regi ster
Intel
DS
628
31:2
19:0
Bits
Bits
Default Value:
Default Value:
7:1
0
0
®
6300ESB I/O Controller Hub
Lockable:
Lockable:
Device:
Device:
Preload_Value_2 [19:0]
Offset:
Offset:
Interrupt Active:
Watchdog Timer
Register
Reserved
Reserved
29
Base + 04h
FFFFFh
No
Name
29
Base + 08h
00h
No
Name
Reserved.
Use this register to hold the preload value for the WDT Timer.
The Value in the Preload Register is automatically transferred
into the 35-bit down-counter every time the WDT enters the
second stage.
NOTE: The value loaded into the preload register needs to be
Please refer to
for details on how to change the value of this register.
Reserved.
(1
down-counter reaches zero. An interrupt will be generated if
WDT_INT_TYPE is configured to do so (See WDT
Configuration Register).
This is a sticky bit and is only cleared by writing a 1.
0 = No Interrupt
1 = Interrupt Active
NOTE: This bit is not set in free-running mode.
st
Stage) This bit is set when the first stage of the 35-bit
one less than the intended period, as the timer makes
use of zero-based counting (i.e., zero is counted as
part of the decrement).
Section 16.5.2, “Register Unlocking Sequence”
Power Well:
Power Well:
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
4
Read-Write
32-bit
Core
4
Read-Write Clear
8-bit
Core
Order Number: 300641-004US
Intel
®
6300ESB ICH—16
November 2007
Access
Access
RWC
R/W
RO
RO