NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 3

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

—Intel
Intel
Product Features
November 2007
Order Number: 300641-004US
®
6300ESB ICH
®
6300ESB I/O Controller Hub
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8-Bit Hub Interface
PCI-X Bus I/F
PCI Bus I/F
Integrated IDE Controller
Integrated Serial ATA Host Controllers
— 266 Mbyte/s maximum throughput
— Parallel Termination scheme for longer
— Supports Lower Voltages as per Hub
— Supports PCI-X Rev 1.0 Specification at
— Supports PCI Rev 2.2 Specification at 33
— Support external master devices on PCI
— 4 @ PCI 33 MHz
— 2 @ PCI 64/66 MHz
— 4 @ PCI-X 64/66 MHz (two slots and
— Support for 64-bit addressing on PCI-X
— Supports PCI 32b/33 MHz
— 120 Mbyte/s throughput
— Supports PCI Rev 2.2 Specification at 33
— Supports 4 external master devices @
— Support for 44-bit addressing on PCI
— 4 slots supported
— Supports “Native Mode” Register and
— Supports faster PIO timings for non-
— Independent timing of up to four drives,
— Supports Ultra 100 DMA Mode Transfers
— PIO Mode four transfers up to 14
— Independent DMA operation on two
— Data transfer rates up to 150 Mbyte/s
— Alternate Device ID and RAID Class
—
trace lengths
Interface 1.5 spec
66 MHz
MHz
two soldered down devices)
using DAC protocol
MHz
33 MHz
using DAC protocol.
Interrupts
data cycles
with separate Primary and Secondary
IDE cable connections
up to 100 Mbytes/s for reads from disk;
88.88 Mbytes/s for writes to disk, as
well as Ultra66 and Ultra33 DMA modes.
Mbytes/s
ports
Code option for support of Soft RAID
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Power Management Logic
External Glue Integration
Enhanced Hub I/F buffers improve routing
flexibility (Not available with all Memory
Controller Hubs)
Firmware Hub (FWH) I/F supports BIOS
Memory size up to 8 Mbytes
Low Pin Count (LPC) I/F
Enhanced DMA Controller
Real-Time Clock
System TCO Reduction Circuits
— ACPI 1.0 compliant
— ACPI-defined power states S1 (Stop
— ACPI Power Management Timer
— SMI# Generation
— PCI PME#
— Supports THRMTRIP# input,
— Support for APM-based legacy power
— Integrated Pull-up, Pull-down and Series
— Integrated Pull-down and Series
— New: No ISA/X-Bus support
— Allows connections of devices such as
— Supports two Master/DMA devices
— Memory size up to 8 Mbytes
— Two cascaded 8237 DMA controllers
— Supports LPC DMA
— Supports DMA Collection Buffer to
— 256-byte battery-backed CMOS RAM
— Timers to generate SMI# and Reset
— Interrupt capability to OS-specific
— Alert On Lan (AOL) to enable heartbeats
— Supports CPU BIST
— Supports ability to disable external
Grant), S3 (STR), S4 (STD), S5 (SOFF)
SYS_RESER# input and SLP_S4#
output
management for non-ACPI
implementations
Termination resistors on IDE, CPU I/F
resistors on USB
Super I/O, microcontrollers, customers
ASICs
provide
Type-F DMA performance for all DMA
channels
upon detection of system hang
manageability extension and OS
capability to call TCO BIOS Timers to
detect improper CPU reset
and system event reporting via LAN
controller
devices
Intel
®
6300ESB I/O Controller Hub
DS
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