NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 11

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Contents—Intel
November 2007
Order Number: 300641-004US
5.12
5.13
5.14
5.11.7 Sleep States ........................................................................................ 155
5.11.8 Thermal Management ........................................................................... 158
5.11.9 Event Input Signal Usage ...................................................................... 159
5.11.10 ALT Access Mode .................................................................................. 162
5.11.11 System Power Supplies, Planes, and Signals ............................................ 165
5.11.12 Clock Generators.................................................................................. 167
5.11.13 Legacy Power Management Theory of Operation ....................................... 168
System Management (D31:F0).......................................................................... 168
5.12.1 Overview of System Management Functions............................................. 168
5.12.2 TCO Signal Usage................................................................................. 169
5.12.3 TCO Theory of Operation ....................................................................... 170
5.12.4 Heartbeat and Event Reporting through SMLink/SMbus ............................. 172
General Purpose I/O ........................................................................................ 176
5.13.1 GPIO Mapping...................................................................................... 176
5.13.2 Power Wells......................................................................................... 178
5.13.3 SMI# and SCI Routing .......................................................................... 178
5.13.4 Triggering ........................................................................................... 178
IDE Controller (D31:F1) ................................................................................... 178
5.14.1 Overview ............................................................................................ 178
5.14.2 PIO Transfers ...................................................................................... 179
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6300ESB ICH
5.11.6.3 STPCLK# Implementation Notes ............................................... 154
5.11.7.1 Sleep State Overview .............................................................. 155
5.11.7.2 Initiating Sleep State............................................................... 155
5.11.7.3 Exiting Sleep States ................................................................ 156
5.11.7.4 Sx-G3-Sx, Handling Power Failures ........................................... 157
5.11.8.1 THRM# Signal ........................................................................ 158
5.11.8.2 THRM# Initiated Passive Cooling ............................................... 158
5.11.8.3 THRM# Override Software Bit ................................................... 159
5.11.8.4 Processor Initiated Passive Cooling (Via Programmed
5.11.8.5 Active Cooling ........................................................................ 159
5.11.9.1 PWRBTN# - Power Button ........................................................ 159
5.11.9.2 RI# - Ring Indicate ................................................................. 160
5.11.9.3 PME# - PCI Power Management Event ....................................... 161
5.11.9.4 SYS_RESET# Signal ................................................................ 161
5.11.9.5 THRMTRIP# Signal .................................................................. 161
5.11.10.1Write Only Registers with Read Paths in ALT Access Mode ............ 163
5.11.10.2Programmable Interrupt Controller (PIC) Reserved Bits................ 164
5.11.10.3Read-Only Registers with Write Paths in ALT Access Mode ............ 165
5.11.11.1Power Plane Control with SLP_S3#, SLP_S4# and SLP_S5# ......... 165
5.11.11.2PWROK Signal ........................................................................ 165
5.11.11.3VRMPWRGD Signal .................................................................. 166
5.11.11.4Controlling Leakage and Power Consumption during Low-Power States
5.11.13.1Overview ............................................................................... 168
5.11.13.2APM Feature Notes.................................................................. 168
5.12.2.1 Intruder# Signal ..................................................................... 169
5.12.2.2 Pin Straps .............................................................................. 169
5.12.2.3 SMLINK Signals ...................................................................... 169
5.12.3.1 Overview ............................................................................... 170
5.12.3.2 Detecting a System Lockup ...................................................... 170
5.12.3.3 Handling an OS Lockup............................................................ 170
5.12.3.4 Handling an Intruder ............................................................... 171
5.12.3.5 Detecting Improper FWH Programming ...................................... 171
5.12.3.6 Handling an ECC Error or Other Memory Error ............................ 171
5.12.4.1 Overview ............................................................................... 172
5.14.2.1 Overview ............................................................................... 179
Duty Cycle on STPCLK#).......................................................... 159
167
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6300ESB I/O Controller Hub
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