NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 271

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
Figure 27. SDIN Wake Signaling
5.20.4
5.20.5
November 2007
Order Number: 300641-004US
®
6300ESB ICH
The minimum AC_SDIN wake up pulse width is 1 us. The rising edge of SDATA_IN
(SDATA_IN(0) or SDATA)IN(1) for split partitioned implementation) causes the audio
controller to sequence through its AC-link “warm reset” and signal PME# to the
system’s ACPI controller. The primary codec must wait to sample AC_SYNC high and
low before restarting BIT_CLK as diagrammed in Figure 6-24. The codec that signaled
the wake event must keep its AC_SDIN high until it has sampled AC_SYNC having gone
high, and then low.
The AC-link protocol provides for a cold reset and a warm reset. The type of reset used
depends on the system’s current power down state. Unless a cold or register reset (a
write to the Reset register in the codec) is performed, wherein the AC‘97 codec
registers are initialized to their default values, registers are required to keep state
during all power down modes.
Once powered down, activation of the AC-link through re-assertion of the AC_SYNC
signal must not occur for a minimum of four audio frame times following the frame in
which the power down was triggered. When AC-link powers up, it indicates readiness
via the codec ready bit.
AC‘97 Cold Reset
A cold reset is achieved by asserting AC_RST# for 1 us. By driving AC_RST# low,
BIT_CLK, and SDOUT will be activated and all codec registers will be initialized to their
default power on reset values.
AC_RST# is an asynchronous AC‘97 input to the codec.
AC‘97 Warm Reset
A warm reset will re-activate the AC-link without altering the current codec register
values. A warm reset is signaled by driving AC_SYNC high for a minimum of 1us in the
absence of BIT_CLK.
Within normal frames, AC_SYNC is a synchronous AC‘97 input to the codec. However,
in the absence of BIT_CLK, AC_SYNC is treated as an asynchronous input to the codec
used in the generation of a warm reset.
The codec must not respond with the activation of BIT_CLK until AC_SYNC has been
sampled low again by the codec. This will prevent the false detection of a new frame.
BIT_CLK
SDOUT
SDIN
SYNC
prev. frame
prev. frame
slot 12
slot 12
TAG
TAG
Power Down
Write to
Frame
0x20
Data
PR4
Sleep State
Wake Event
Intel
®
6300ESB I/O Controller Hub
TAG
TAG
New Audio
Frame
Slot 1
Slot 1
Slot 2
Slot 2
271
DS