NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 641

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

17—Intel
Table 574. IND—Index Register
17.2.3
Table 575. DAT—Data Register
17.2.4
November 2007
Order Number: 300641-004US
Bits
Bits
Default Value:
Default Value:
7:0
7:0
Address:
Address:
Memory
Note: This is a 32-bit register specifying the data to be read or written to the register pointed
Memory
Note: Writes to this register are only allowed by the processor and by masters on the Intel
Device:
Device:
®
6300ESB ICH
APIC Index
APIC Data
DAT—Data Register
to by the Index register. This register may only be accessed in DWORD quantities.
IRQPA—IRQ Pin Assertion Register
The IRQ Pin Assertion Register is present to provide a mechanism to scale the number
of interrupt inputs into the I/O APIC without increasing the number of dedicated input
pins. When a device that supports this interrupt assertion protocol requires interrupt
service, that device will issue a write to this register. Bits 4:0 written to this register
contain the IRQ number for this interrupt. The only valid values are 0-23. Bits 31:5 are
ignored. To provide for future expansion, peripherals should always write a value of 0
for Bits 31:5.
6300ESB ICH’s PCI bus. Writes by devices on PCI buses above the Intel
(e.g., a PCI segment on a P64H) are not supported.
29
FEC0_0000h
00h
Name
29
FEC0_0010h
00000000h
Name
This is an 8-bit pointer into the I/O APIC register table.
This is a 32-bit register for the data to be read or written to
the APIC indirect register pointed to by the Index register.
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
5
Read/Write
8-bit
5
Read/Write
32-bit
Intel
®
6300ESB I/O Controller Hub
®
6300ESB ICH
Access
Access
R/W
R/W
641
®
DS