NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 520

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 420. PORTSC- Port N Status and Control (Sheet 3 of 4)
Intel
DS
520
Bits
Default Value:
7
6
5
®
6300ESB I/O Controller Hub
Device:
Offset:
Overcurrent Change
Force Port Resume
Suspend
29
Port 0:CAPLENGTH+44-47h
Port 1: CAPLENGTH+48-4Bh
Port 2: CAPLENGTH+4C-4Fh
Port 3: CAPLENGTH+50-53h
00003000h
Name
1 = Port in suspend state. 0 = Port not in suspend state.
Default = 0. Port Enabled Bit and Suspend bit of this register
define the port states as follows:
Bits [Port Enabled, Suspend] Port State
When in suspend state, downstream propagation of data is
blocked on this port, except for port reset. Note that the bit
status does not change until the port is suspended and that
there may be a delay in suspending a port depending on the
activity on the port.
The host controller will unconditionally set this bit to a ’0’
when software sets the Force Port Resume bit to a ’0’ (from a
‘1’). A write of ’0’ to this bit is ignored by the host controller.
When host software sets this bit to a ’1’ when the port is not
enabled (i.e., Port enabled bit is a ’0’), the results are
undefined.
1 = Resume detected/driven on port. 0 = No resume (K-
state) detected/driven on port. Default = 0.
Software sets this bit to a ’1’ to drive resume signaling. The
Host Controller sets this bit to a ’1’ when a J-to-K transition is
detected while the port is in the Suspend state. When this bit
transitions to a ’1’ because a J-to-K transition is detected, the
Port Change Detect bit in the USBSTS register is also set to a
’1’. When software sets this bit to a ’1’, the host controller
must not set the Port Change Detect bit.
Note that when the EHCI controller owns the port, the
resume sequence follows the defined sequence documented
in the USB Specification Revision 2.0. The resume signaling
(Full-speed 'K') is driven on the port as long as this bit
remains a ’1’. Software must appropriately time the Resume
and set this bit to a ’0’ when the appropriate amount of time
has elapsed. Writing a ’0’ (from ‘1’) causes the port to return
to high-speed mode (forcing the bus below the port into a
high-speed idle). This bit will remain a ’1’ until the port has
switched to the high-speed idle.
Default = 0. 1 = This bit gets set to a ’1’ when there is a
change to Over-current Active. Software clears this bit by
writing a ’1’ to this bit position.
The functionality of this bit is not dependent upon the port
owner.
0X
10
11
Description
Attribute:
Function:
Size:
Disable
Enable
Suspend
7
Read/Write
32-bit
Order Number: 300641-004US
Intel
®
6300ESB ICH—11
November 2007
Access
R/WC
R/W
R/W