NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 458

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Intel
DS
458
Bits
Default Value:
2
1
0
®
Table 349. BMIS[P,S]—Bus Master IDE Status Register
6300ESB I/O Controller Hub
Device:
Offset:
Bus Master IDE Active
Interrupt
31
Primary: 02h
Secondary: 0Ah
00h
Name
(ACT)
Error
Software may use this bit to determine if an IDE device has
asserted its interrupt line (IRQ 14 for the Primary channel,
and IRQ 15 for Secondary).
0 = This bit is cleared by software writing a '1' to the bit
1 = Set by the rising edge of the IDE interrupt line,
0 = This bit is cleared by software writing a '1' to the bit
1 = This bit is set when the controller encounters a target
0 = This bit is cleared by the Intel
1 = Set by the Intel
position. When this bit is cleared while the interrupt is
still active, this bit will remain clear until another
assertion edge is detected on the interrupt line.
regardless of whether or not the interrupt is masked in
the 8259 or the internal I/O APIC. When this bit is read
as a one, all data transferred from the drive is visible in
system memory.
position.
abort or master abort when transferring data on PCI.
last transfer for a region is performed, where EOT for that
region is set in the region descriptor. It is also cleared by
the Intel
the Command register. When this bit is read as a zero, all
data transferred from the drive during the previous bus
master command is visible in system memory, unless the
bus master command was aborted.
written to the Command register.
®
6300ESB ICH when the Start bit is cleared in
®
6300ESB ICH when the Start bit is
Description
Attribute:
Function:
Size:
®
6300ESB ICH when the
1
Read/Write Clear
8-bit
Order Number: 300641-004US
Intel
®
6300ESB ICH—9
November 2007
Access
R/WC
R/WC
RO