NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 214

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5.17.7
5.17.7.1 Overview
5.17.7.2 Transaction Based Interrupts
Intel
DS
214
®
6300ESB I/O Controller Hub
USB Interrupts
There are two general groups of USB interrupt sources, those resulting from execution
of transactions in the schedule, and those resulting from an Intel
operation error. All transaction-based sources may be masked by software through the
Intel
descriptors may be marked to generate an interrupt on completion.
When the Intel
PIRQ[A]# pin for USB function #0, PIRQ[D]# pin for USB function #1 until all sources
of the interrupt are cleared. In order to accommodate some operating systems, the
Interrupt Pin register must contain a different value for each function of this new multi-
function device.
These interrupts are not signaled until after the status for the last complete transaction
in the frame has been written back to host memory. This ensures that software may
safely process through (Frame List Current Index -1) when it is servicing an interrupt.
CRC Error/Time-Out
A CRC/Time-Out error occurs when a packet transmitted from the Intel
to a USB device or a packet transmitted from a USB device to the Intel
generates a CRC error. The Intel
from the USB device or by the Intel
on reception of the packet. Additionally, a USB bus time-out occurs when USB devices
do not respond to a transaction phase within 19-bit times of an EOP. Either of these
conditions will cause the C_ERR field of the TD to decrement.
When the C_ERR field decrements to zero, the following occurs:
When the CRC/Time out interrupt is enabled in the Interrupt Enable register, a
hardware interrupt will be signaled to the system.
Interrupt on Completion
Transfer Descriptors contain a bit that may be set to cause an interrupt on their
completion. The completion of the transaction associated with that block causes the
USB Interrupt bit in the HC Status Register to be set at the end of the frame in which
the transfer completed. When a TD is encountered with the IOC bit set to 1, the IOC bit
in the HC Status register is set to 1 at the end of the frame when the active bit in the
TD is set to 0 (even when it was set to zero when initially read).
When the IOC Enable bit of Interrupt Enable register (bit 2 of I/O offset 04h) is set, a
hardware interrupt is signaled to the system. The USB Interrupt bit in the HC status
register is set either when the TD completes successfully or because of errors. When
the completion is because of errors, the USB Error bit in the HC status register is also
set.
Short Packet Detect
•
•
•
•
The Active bit in the TD is cleared
The Stalled bit in the TD is set
The CRC/Time-out bit in the TD is set.
At the end of the frame, the USB Error Interrupt bit is set in the HC status register.
®
6300ESB ICH’s Interrupt Enable register. Additionally, individual transfer
®
6300ESB ICH drives an interrupt for USB, it internally drives the
®
6300ESB ICH is informed of this event by a time-out
®
6300ESB ICH’s CRC checker generating an error
Order Number: 300641-004US
®
Intel
6300ESB ICH
®
®
®
6300ESB ICH—5
6300ESB ICH
6300ESB ICH
November 2007