NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 313

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8—Intel
8.1.2
Table 182. Offset 02 - 03h: DID—Device ID Register (LPC I/F—D31:F0)
8.1.3
Table 183. Offset 04 - 05h: PCICMD—PCI COMMAND Register (LPC I/F—D31:F0)
November 2007
Order Number: 300641-004US
15:0
15:1
Bits
Bits
Default Value:
Default Value:
0
9
8
7
6
5
4
3
2
1
0
Lockable:
Lockable:
®
Device:
Device:
WCC: Wait Cycle Control
PMWE: Postable Memory
VPS: VGA Palette Snoop
BME: Bus Master Enable
Offset:
Offset:
FBE: Fast Back to Back
6300ESB ICH
IOE: I/O Space Enable
MSE: Memory Space
SCE: Special Cycle
SERR_EN: SERR#
PER: Parity Error
Device ID Value
Write Enable
Offset 02 - 03h: DID—Device ID Register (LPC I/
F—D31:F0)
Offset 04 - 05h: PCICMD—PCI COMMAND Register
(LPC I/F—D31:F0)
Response
Reserved
Enable
Enable
Enable
Enable
31
02-03h
25A1h
No
Name
31
04-05h
000Fh
No
Name
This is a 16-bit value assigned to the Intel
Bridge.
Reserved.
Hardwired to 0.
0 = Disable.
1 = Enable. Allow SERR# to be generated.
Hardwired to 0.
0 = No action is taken when detecting a parity error.
1 = The processor will take normal action when a parity error
Hardwired to 0
Hardwired to 0
Hardwired to 1.
Hardwired to 1 to indicate that bus mastering cannot be
disabled for function 0 (DMA/ISA Master)
Hardwired to 1 to indicate that memory space cannot be
disabled for Function 0 (LPC I/F)
Hardwired to 1 to indicate that the I/O space cannot be
disabled for function 0 (LPC I/F)
is detected.
Power Well:
Power Well:
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
0
Read-Only
16-bit
Core
0
Read/Write
16-bit
Core
®
6300ESB ICH LPC
Intel
®
6300ESB I/O Controller Hub
Access
Access
RO
RO
RO
RO
RO
RO
RO
313
DS