NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 759

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

20—Intel
20.1.31 Offset 88 - 89h: MD—Message Signaled Interrupt
20.1.32 Offset 90h: MAP—Address Map (SATA–D31:F2)
November 2007
Order Number: 300641-004US
15:0
Bits
Bits
Default Value:
Default Value:
7:3
2:0
Table 690. Offset 88 - 89h: MD—Message Signaled Interrupt Message Data
Table 691. Offset 90h: MAP—Address Map (SATA–D31:F2)
Device:
Device:
®
Offset:
Offset:
6300ESB ICH
Data (DATA)
Map Value
Message Data (SATA–D31:F2)
(SATA–D31:F2)
Reserved
31
88-89h
0000h
Name
31
90h
00h
Name
This field is programmed by system software when MSI is
enabled. Its content is driven onto the lower word (PCI
AD[15:0]) during the data phase of the MSI memory write
transaction.
Reserved.
The value of these bits indicate the address range the SATA
port responds to, and whether or not the SATA and IDE
functions are combined.
000 = Non-combined. P0 is primary master. P1 is secondary
master.
001 = Non-combined. P0 is secondary master. P1 is primary
master.
100 = Combined. P0 is primary master. P1 is primary slave.
P-ATA is secondary.
101 = Combined. P0 is primary slave. P1 is primary master.
P-ATA is secondary.
110 = Combined. P-ATA is primary. P0 is secondary master.
P1 is secondary slave.
111 = Combined. P-ATA is primary. P0 is secondary slave. P1
is secondary master.
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
2
Read/Write
16-bit
2
Read-Only, Read/Write
8-bit
Intel
®
6300ESB I/O Controller Hub
Access
Access
R/W
759
DS