NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 103

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
5.3
5.3.1
Figure 11. Intel
November 2007
Order Number: 300641-004US
®
6300ESB ICH
Bus Master Device Mapping and START Fields
Bus Masters must have a unique START field. In the case of the Intel
which supports two LPC bus masters, it will drive 0010 for the START field for grants to
bus master #0 (requested through LDRQ[0]#) and 0011 for grants to bus master #1
(requested through LDRQ[1]#.). Thus no registers are needed to config the START
fields for a particular bus master.
BIOS Mapping and START Fields
To reduce decoding logic in the FWH, the Intel
field for each EPROM. To do this, the Intel
assign a particular BIOS range to a particular IDSEL field.
DMA Operation (D31:F0)
DMA Overview
The Intel
The DMA controller has registers that are fixed in the lower 64 Kbyte of I/O space. The
DMA controller is configured using registers in the PCI config space. These registers
allow configuration of individual channels for use by LPC DMA.
The DMA circuitry incorporates the functionality of two 8237 DMA controllers with
seven independently programmable channels
corresponds to DMA channels 0-3 and DMA Controller 2 (DMA-2) corresponds to
channels 5-7. DMA channel 4 is used to cascade the two controllers and will default to
cascade mode in the DMA Channel Mode (DCM) Register. Channel 4 is not available for
any other purpose. In addition to accepting requests from DMA slaves, the DMA
controller also responds to requests that software initiates. Software may initiate a
DMA service request by setting any bit in the DMA Channel Request Register to 1.
Each DMA channel is hardwired to the compatible settings for DMA device size:
channels [3:0] are hardwired to 8-bit, count-by-bytes transfers, and channels [7:5] are
hardwired to 16-bit, count-by-words (address shifted) transfers.
The Intel
compatible specification. Each channel includes a 16-bit ISA-Compatible Current
Register which holds the 16 least-significant bits of the 24-bit address, an ISA-
Compatible Page Register which contains the eight next most significant bits of
address.
The DMA controller also features refresh address generation, and autoinitialization
following a DMA termination.
®
6300ESB ICH DMA Controller
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®
6300ESB ICH supports LPC DMA through LPC, similar to ISA DMA.
6300ESB ICH provides 24-bit addressing in compliance with the ISA-
Channel 1
Channel 2
Channel 3
Channel 0
DMA-1
®
6300ESB ICH has configuration registers to
(Figure
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Channel 4
Channel 5
Channel 6
Channel 7
6300ESB ICH will use a unique IDSEL
11). DMA Controller 1 (DMA-1)
Intel
®
DMA-2
6300ESB I/O Controller Hub
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6300ESB ICH,
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