NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 375

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8—Intel
Table 259. Delivery Mode Encoding
8.6
8.6.1
November 2007
Order Number: 300641-004US
®
6300ESB ICH
Real Time Clock Registers
I/O Register Address Map
The RTC internal registers and RAM are organized as two banks of 128 bytes each,
called the standard and extended banks. The first 14 bytes of the standard bank
contain the RTC time and date information along with four registers, A - D, that are
used for configuration of the RTC. The extended bank contains a full 128 bytes of
battery backed SRAM, and will be accessible even when the RTC module is disabled
(through the RTC configuration register). Registers A-D do not physically exist in the
RAM.
All data movement between the host processor and the real-time clock is done through
registers mapped to the standard I/O space. The register map appears in
Bits
000
001
010
011
100
101
110
111
Fixed: Deliver the signal on the INTR signal of all processor cores listed in the
destination. Trigger Mode may be edge or level.
Lowest Priority: Deliver the signal on the INTR signal of the processor core that is
executing at the lowest priority among all the processors listed in the specified
destination. Trigger Mode may be edge or level.
SMI (System Management Interrupt): Requires the interrupt to be programmed
as edge triggered. The vector information is ignored but must be programmed to all
zeroes for future compatibility. -- not supported.
Reserved
NMI: Deliver the signal on the NMI signal of all processor cores listed in the
destination. Vector information is ignored. NMI is treated as an edge triggered
interrupt even when it is programmed as level triggered. For proper operation this
redirection table entry must be programmed to edge triggered. The NMI delivery
mode does not set the RIRR bit. Once the interrupt is detected, it will be sent over
the APIC bus. When the redirection table is incorrectly set to level, the loop count
will continue counting through the redirection table addresses. Once the count for
the NMI pin is reached again, the interrupt will be sent over the APIC bus again. --
not supported.
INIT: Deliver the signal to all processor cores listed in the destination by asserting
the INIT signal. All addressed local APICs will assume their INIT state. INIT is
always treated as an edge triggered interrupt even when programmed as level
triggered. For proper operation this redirection table entry must be programmed to
edge triggered. The INIT delivery mode does not set the RIRR bit. Once the
interrupt is detected, it will be sent over the APIC bus. When the redirection table is
incorrectly set to level, the loop count will continue counting through the redirection
table addresses. Once the count for the INIT pin is reached again, the interrupt will
be sent over the APIC bus again. -- not supported.
Reserved.
ExtINT: Deliver the signal to the INTR signal of all processor cores listed in the
destination as an interrupt that originated in an externally connected 8259A
compatible interrupt controller. The INTA cycle that corresponds to this ExtINT
delivery will be routed to the external controller that is expected to supply the
vector. Requires the interrupt to be programmed as edge triggered.
Description
Intel
®
6300ESB I/O Controller Hub
Table
260.
375
DS