NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 625

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

16—Intel
16.4.15 Offset 60 - 61h: WDT Configuration Register
Table 550. Offset 60 - 61h: WDT Configuration Register
16.4.16 Offset 68h: WDT Lock Register
November 2007
Order Number: 300641-004US
15:6
Bits
Default Value:
4:3
1:0
5
2
Lockable:
Device:
®
Offset:
WDT_OUTPUT: Output
6300ESB ICH
WDT_PRE_SEL:
Prescaler Select
WDT_INT_TYPE
Reserved
Reserved
Enable
29
60 - 61h
00h
No
Name
Reserved.
This bit indicates whether or not the WDT will toggle the
external WDT_TOUT# pin when the WDT times out.
0 = Enabled (Default)
1 = Disabled
This signal is muxed with GPIO32.
Reserved.
The WDT provides two options for prescaling the main down-
counter. The preload values are loaded into the main down-
counter right justified. The prescaler adjusts the starting
point of the 35-bit down counter.
0 = The 20-bit Preload Value is loaded into bits 34:15 of the
1 = The 20-bit Preload Value is loaded into bits 24:5 of the
NOTE: Timeout value is determined by the preload value
The WDT timer supports programmable routing of interrupts.
The set of bits allows the user to choose the type of interrupt
desired when the WDT reached the end of the first stage
without being reset.
00 = IRQ (APIC 1, INT 10) (Default)
01 = Reserved
10 = SMI
11 = Disabled
IRQ is Active low, level triggered
main down counter. The resulting timer clock is the PCI
Clock (33 MHz) divided by 2
generated is 1 KHz, (Default)
main down counter. The resulting timer clock is the PCI
Clock (33 MHz) divided by 2
generated is 1 MHz.
multiplied by the clock period.
Power Well:
Description
Attribute:
Function:
Size:
15
5
. The approximate clock
. The approximate clock
4
Read, Write
16-bit
Core
Intel
®
6300ESB I/O Controller Hub
Access
R/W
R/W
R/W
RO
RO
625
DS