NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 513

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

11—Intel
Table 413. Offset CAPLENGTH + 04 - 07h: USB EHCI STS—USB EHCI Status (Sheet
November 2007
Order Number: 300641-004US
Bits
Default Value:
4
3
2
1
0
Device:
®
USB Interrupt (USBINT)
Offset:
6300ESB ICH
Port Change Detect
USB Error Interrupt
Frame List Rollover
Host System Error
(USBERRINT)
2 of 2)
29
CAPLENGTH + 04-07h
00001000h
Name
The Host Controller sets this bit to ’1’ when a serious error
occurs during a host system access involving the Host
Controller module. A hardware interrupt is generated to the
system. Memory read cycles initiated by the EHC that receive
any status other than Successful will result in this bit being
set.
When this error occurs, the Host Controller clears the Run/Stop bit in
the Command register to prevent further execution of the scheduled
TDs. A hardware interrupt is generated to the system (when enabled in
the Interrupt Enable Register).
The Host Controller sets this bit to a ’1’ when the Frame List
Index rolls over from its maximum value to ’0’. Since the
Intel
Size, the Frame List Index rolls over every time FRNUM[13]
toggles.
The Host Controller sets this bit to a ’1’ when any port for
which the Port Owner bit is set to ’0’ has a change bit
transition from a ’0’ to a ’1’ or a Force Port Resume bit
transition from a ’0’ to a ’1’ as a result of a J-K transition
detected on a suspended port.
This bit is allowed to be maintained in the Auxiliary power
well. Alternatively, it is also acceptable that on a D3 to D0
transition of the EHCI HC device, this bit is loaded with the
OR of all of the PORTSC change bits (including: Force port
resume, over-current change, enable/disable change and
connect status change). Regardless of the implementation,
whenever this bit is readable (i.e., in the D0 state), it must
provide a valid view of the Port Status registers.
The Host Controller sets this bit to ’1’ when completion of a
USB transaction results in an error condition (e.g., error
counter underflow). When the TD on which the error interrupt
occurred also had its IOC bit set, both this bit and Bit ’0’ are
set. See the EHCI specification for a list of the USB errors that
will result in this interrupt being asserted.
The Host Controller sets this bit to ’1’ when the cause of an
interrupt is a completion of a USB transaction whose Transfer
Descriptor had its IOC bit set.
The Host Controller also sets this bit to ’1’ when a short
packet is detected (actual number of bytes received was less
than the expected number of bytes).
®
6300ESB ICH only supports the 1024-entry Frame List
Description
Attribute:
Function:
Size:
7
Read/Write Clear
32-bit
Intel
®
6300ESB I/O Controller Hub
Access
R/WC
R/WC
R/WC
R/WC
R/WC
513
DS