NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 36

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Intel
DS
36
164
165
166
167
168
169
170
171
172
173
174 Offset 58 - 5Bh: D30_PNE — PERR#_NMI_ENABLE Register (HUB-PCI—D30:F0)............. 307
175
176
177
178
179
180
181
182 Offset 02 - 03h: DID—Device ID Register (LPC I/F—D31:F0) ........................................ 313
183 Offset 04 - 05h: PCICMD—PCI COMMAND Register (LPC I/F—D31:F0) ........................... 313
184 Offset 06 - 07h: PCISTA—PCI Device Status (LPC I/F—D31:F0) .................................... 314
185 Offset 08h: RID—Revision ID Register (LPC I/F—D31:F0) ............................................ 315
186 Offset 09h: PI—Programming Interface (LPC I/F—D31:F0) ........................................... 315
187 Offset 0Ah: SCC—Sub-Class Code Register (LPC I/F—D31:F0) ...................................... 315
188 Offset 0Bh: BCC—Base-Class Code Register (LPC I/F—D31:F0)..................................... 316
189 Offset 0Eh: HEADTYP—Header Type Register (LPC I/F—D31:F0) ................................... 316
190 Offset 40 - 43h: PMBASE—ACPI Base Address (LPC I/F—D31:F0) ................................. 317
191 Offset 44h: ACPI_CNTL—ACPI Control (LPC I/F—D31:F0) ............................................ 317
192 Offset 4E - 4Fh: BIOS_CNTL (LPC I/F—D31:F0) .......................................................... 319
193 Offset 54h: TCO_CNTL—TCO Control (LPC I/F—D31:F0) .............................................. 320
194 Offset 58h - 5Bh: GPIO_BASE—GPIO Base Address (LPC I/F—D31:F0) .......................... 321
195 Offset 5Ch: GPIO_CNTL—GPIO Control (LPC I/F—D31:F0) ........................................... 321
196 Offset PIRQA - 60h: PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control (LPC I/F—D31:F0) .. 322
197 Offset 64h: SERIRQ_CNTL—Serial IRQ Control (LPC I/F—D31:F0) ................................. 323
198 Offset PIRQE - 68h: PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control (LPC I/F—D31:F0) ... 324
199 Offset 88h: D31_ERR_CFG—Device 31 Error Config Register (LPC I/F—D31:F0).............. 325
200 Offset 8Ah: D31_ERR_STS—Device 31 Error Status Register (LPC I/F—D31:F0).............. 326
201 Offset 90h - 91h: PCI_DMA_CFG—PCI DMA Configuration (LPC I/F—D31:F0).................. 326
202 Offset D0h - D3h: GEN_CNTL—General Control Register (LPC I/F—D31:F0).................... 327
203 Offset D4h: GEN_STA—General Status (LPC I/F—D31:F0)............................................ 329
204 Offset D5h: BACK_CNTL—Backed Up Control (LPC I/F—D31:F0) ................................... 330
205 Offset D8h: RTC_CONF—RTC Configuration Register (LPC I/F—D31:F0) ......................... 331
206 Offset E0h: COM_DEC—LPC I/F Communication Port Decode Ranges (LPC I/F—D31:F0) .. 332
207 Offset E1h: FDD/LPT_DEC—LPC I/F FDD and LPT Decode Ranges (LPC I/F—D31:F0) ....... 333
208 Offset E2h: SND_DEC—LPC I/F Sound Decode Ranges (LPC I/F—D31:F0) ...................... 334
209 Offset E3h: FWH_DEC_EN1—FWH Decode Enable 1 Register (LPC I/F—D31:F0).............. 335
210 Offset E4h - E5h: GEN1_DEC—LPC I/F Generic Decode Range 1 (LPC I/F—D31:F0) ......... 336
211 Offset E6h - E7h: LPC_EN—LPC I/F Enables (LPC I/F—D31:F0) ..................................... 337
212 Offset E8h: FWH_SEL1—FWH Select 1 Register (LPC I/F—D31:F0) ................................ 339
213 Offset ECh - EDh: GEN2_DEC—LPC I/F Generic Decode Range 2 (LPC I/F—D31:F0) ........ 340
214 Offset EEh - EFh: FWH_SEL2—FWH Select 2 Register (LPC I/F—D31:F0)........................ 341
215 Offset F0h: FWH_DEC_EN2—FWH Decode Enable 2 Register (LPC I/F—D31:F0) .............. 342
®
6300ESB I/O Controller Hub
Offset 22 - 23h: MEMLIM—Memory Limit Register
Offset 24h - 25h: PREF_MEM_BASE—Prefetchable Memory Base Register (HUB-PCI—D30:F0)
298
Offset 26h-27h: PREF_MEM_MLT—Prefetchable Memory Limit Register (HUB-PCI—D30:F0)
299
Offset 30 - 31h: IOBASE_HI—I/O Base Upper 16 Bits Register (HUB-PCI—D30:F0)
Offset 32 - 33h: IOLIM_HI—I/O Limit Upper 16 Bits Register (HUB-PCI—D30:F0)
Offset 3Ch: INT_LINE—Interrupt Line Register (HUB-PCI—D30:F0)
Offset 3E - 3Fh: BRIDGE_CNT—Bridge Control Register (HUB-PCI—D30:F0)
Offset 40 - 43h: HI_CMD—Hub Interface Command Control Register
Offset 44 - 45h: DEVICE_HIDE—Secondary PCI Device Hiding Register (HUB-PCI—D30:F0)
305
Offset 50 - 51h: CNF—Intel® 6300ESB ICH Configuration Register (HUB-PCI—D30:F0)
Offset 70h: MTT—Multi-Transaction Timer Register (HUB-PCI—D30:F0)
Offset 82h: PCI_MAST_STS—PCI Master Status Register (HUB-PCI—D30:F0)
Offset 90h: ERR_CMD—Error Command Register (HUB-PCI—D30:F0)
Offset 92h: ERR_STS—Error Status Register (HUB-PCI—D30:F0)
Offset F8h - FBh: MANID— Manufacturer’s
PCI Configuration Registers (D31:F0)
Offset 00 - 01h: VID—Vendor ID Register (LPC I/F—D31:F0)
........................................................................ 311
ID............................................................. 310
(HUB-PCI—D30:F0)........................... 297
....................................... 312
.................................. 310
Intel
............................... 300
(HUB-PCI—D30:F0). 304
............................ 309
Order Number: 300641-004US
®
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6300ESB ICH—Contents
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November 2007
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