NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 441

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

9—Intel
9.1.8
9.1.9
9.1.10
November 2007
Order Number: 300641-004US
NOTE: This 8-byte I/O space is used in native mode for the Primary Controller’s Command Block.
31:1
15:3
Bits
Bits
Bits
Default Value:
Default Value:
Default Value:
7:0
7:0
2:1
6
0
Table 330. Offset 0Bh: BCC—Base Class Code (IDE—D31:F1)
Table 331. Offset 0Dh: MLT—Master Latency Timer (IDE—D31:F1)
Table 332. Offset 10h - 13h: PCMD_BAR—Primary Command Block Base
®
Device:
Device:
Device:
Resource Type Indicator
Offset:
Offset:
Offset:
6300ESB ICH
Bus Master Latency
Base Class Code
Base Address
Offset 0Bh: BCC—Base Class Code (IDE—D31:F1)
Offset 0Dh: MLT—Master Latency Timer (IDE—
D31:F1)
Offset 10h - 13h: PCMD_BAR—Primary Command
Block
Base Address Register (IDE—D31:F1)
Address Register (IDE—D31:F1)
Reserved
Reserved
31
0Bh
01h
Name
31
0Dh
00h
Name
Name
(RTE)
00000001h
10h-13h
31
01 = Mass storage device
Hardwired to 00h. The IDE controller is implemented
internally, and is not arbitrated as a PCI device, so it does not
need a Master Latency Timer. These bits are fixed at 0.
Reserved.
Base address of the I/O space (8 consecutive I/O locations).
Reserved.
This bit is set to one, indicating a request for IO space. Read-
Only.
Description
Description
Description
Attribute:
Attribute:
Attribute:
Function:
Function:
Function:
Size:
Size:
Size:
1
Read-Only
8-bit
1
Read-Only
8-bit
1
Read/Write
32-bit
Intel
®
6300ESB I/O Controller Hub
Access
Access
Access
R/W
RO
RO
RO
441
DS