NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 762
NHE6300ESB S L7XJ
Manufacturer Part Number
NHE6300ESB S L7XJ
Description
Manufacturer
Intel
Datasheet
1.NHE6300ESB_S_L7XJ.pdf
(848 pages)
Specifications of NHE6300ESB S L7XJ
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20.1.36 STTT—SATA TX Termination Test Register A
20.1.37 STOT — SATA TX Output Test Register (SATA–
Intel
DS
762
15:2
15:2
Bits
Bits
Default Value:
Default Value:
1
0
1
0
®
Table 695. STTT—SATA TX Termination Test Register A (SATA–D31:F2)
Table 696. STOT — SATA TX Output Test Register (SATA–D31:F2)
6300ESB I/O Controller Hub
Address:
Address:
Device:
Device:
Index
Index
Port 1 TX Termination
Port 0 TX Termination
Force ALIGN TX Bit
Test Enable
Test Enable
(SATA–D31:F2)
D31:F2)
Reserved
Reserved
Reserved
31
Index 00h–01h
XXXXh
Name
31
Index 1Eh
XXXXh
Name
Reserved.
Setting this bit will enable testing of the port’s TX
termination. This bit is only to be used for system board
testing.
Setting this bit will enable testing of the port’s TX
termination. This bit is only to be used for system board
testing.
Reserved.
This bit will force the Intel
transmit the SATA ALIGN primitive when set. This bit is only
used for system board testing.
Reserved.
Description
Description
Attribute:
Attribute:
Function:
Function:
®
6300ESB ICH to repeatedly
Size:
Size:
2
Read/Write
16-bit
2
Read/Write
16-bit
Order Number: 300641-004US
Intel
®
6300ESB ICH—20
November 2007
Access
Access
R/W
R/W
R/W
R/W
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