NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 228

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5.18.7.1 Aborts on USB EHCI-Initiated Memory Reads
5.18.8
5.18.8.1 Pause Feature
Intel
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6300ESB I/O Controller Hub
When a read initiated by the EHC is aborted, the EHC treats it as a fatal host error. The
following actions are taken when this occurs:
USB EHCI Power Management
This feature allows platforms, especially mobile systems, to dynamically enter low-
power states during brief periods when the system is idle, i.e., between keystrokes.
This is useful for enabling power management features like C3, C4, and Intel
SpeedStep
states typically are based on the recent history of system bus activity to incrementally
enter deeper power management states. Normally, when the EHC is enabled, it
regularly accesses main memory while traversing the DMA schedules looking for work
to do; this activity is viewed by the power management software as a non-idle system,
thus preventing the power managed states to be entered. Suspending all of the
enabled ports may prevent the memory accesses from occurring, but there is an
inherent latency overhead with entering and exiting the suspended state on the USB
ports that makes this unacceptable for the purpose of dynamic power management. As
a result, the EHCI software drivers are allowed to pause the EHC’s DMA engines when it
knows that the traffic patterns of the attached devices may afford the delay. The pause
only prevents the EHC from generating memory accesses; the SOF packets continue to
be generated on the USB ports (unlike the suspended state).
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The Intel
The Intel
the “Do Complete-Split” execution criteria are not met.
For complete-split transactions in the Periodic list, the “Missed Microframe” bit does
not get set on a control-structure-fetch that fails the late-start test. When
subsequent accesses to that control structure do not fail the late-start test, then
the “Missed Microframe” bit will get set and written back.
The Host System Error status bit is set. See
+ 04 - 07h: USB EHCI STS—USB EHCI Status”
04h, bit 4.
The DMA engines are halted after completing up to one more transaction on the
USB interface.
When enabled (by the Host System Error Enable), an interrupt is generated. See
Section 11.2.2.3, “Offset CAPLENGTH + 08 - 0Bh: USB EHCI INTR—USB EHCI
Interrupt Enable”
When the status is Master Abort, the Received Master Abort bit in configuration
space is set.
regarding offset 06h, bit 13.
When the status is Target Abort, the Received Target Abort bit in configuration
space is set.
regarding offset 06h, bit 12.
When enabled (by the SERR Enable bit in the function’s configuration space, see
Section 11.1.1, “Offset 04 - 05h: Command
Signaled System Error bit is set by the Intel
(internally).
regarding offset 06h,
bit 14.
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technology in the Intel
6300ESB ICH delivers interrupts using PIRQ#[H].
6300ESB ICH does not modify the CERR count on an Interrupt IN when
Section 11.1.2, “Offset 06 - 07h: Device Status”
Section 11.1.2, “Offset 06 - 07h: Device Status”
Section 11.1.2, “Offset 06 - 07h: Device Status”
for information regarding offset 08h, bit 4.
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6300ESB ICH. The policies for entering these
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Section 11.2.2.2, “Offset CAPLENGTH
Register”, offset 04h, bit 8), the
6300ESB ICH when it signals SERR#
for information regarding offset
Order Number: 300641-004US
for information
for information
for information
Intel
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6300ESB ICH—5
November 2007
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