NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 448

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Intel
DS
448
13:1
Bits
Default Value:
15
14
11
2
®
Table 342. IDE_TIM—IDE Timing Register (IDE—D31:F1) (Sheet 1 of 3)
6300ESB I/O Controller Hub
Device:
Offset:
Drive 1 Timing Register
IORDY Sample Point
IDE Decode Enable
Enable (SITRE)
Reserved
31
Primary:
Secondary: 42-43h
0000h
Name
(IDE)
(ISP)
40-41h
Individually enable/disable the Primary or Secondary decode.
The IDE I/O Space Enable bit in the Command register must
be set in order for this bit to have any effect. Additionally,
separate configuration bits are provided (in the IDE I/O
Configuration register) to individually disable the primary or
secondary IDE interface signals, even when the IDE Decode
Enable bit is set.
0 = Disable.
1 = Enables the Intel
This bit effects the IDE decode ranges for both legacy and
native-Mode decoding. It also effects the corresponding
primary or secondary memory decode range for IDE
Expansion.
0 = Use bits 13:12, 9:8 for both drive 0 and drive 1.
1 = Use bits 13:12, 9:8 for drive 0, and use the Slave IDE
The setting of these bits determine the number of PCI clocks
between IDE IOR#/IOW# assertion and the first IORDY
sample point.
00 = 5 clocks
01 = 4 clocks
10 = 3 clocks
11 = Reserved
Reserved.
associated Command Blocks (1F0-1F7h for primary, 170-
177h for secondary) and Control Block (3F6h for primary
and 376h for secondary).
Timing register for drive 1
®
6300ESB ICH to decode the
Description
Attribute:
Function:
Size:
1
Read/Write
16-bit
Order Number: 300641-004US
Intel
®
6300ESB ICH—9
November 2007
Access
R/W
R/W