NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 470

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 368. Offset C0 - C1h: USB_LEGKEY—USB Legacy Keyboard/ Mouse Control
Intel
DS
470
Bits
Default Value:
15
14
13
12
11
10
®
6300ESB I/O Controller Hub
Device:
Offset:
SMI Caused by Port 64
SMI Caused by Port 64
Pass-through (SMIBY-
Interrupt (SMIBYUSB)
SMI Caused by End of
PCI Interrupt Enable
Write (TRAPBY64W)
SMI Caused by USB
Read (TRAPBY64R)
(USBPIRQEN)
Register (USB—D29:F0/F1) (Sheet 1 of 3)
Reserved
ENDPS)
29
C0-C1h
2000h
Name
Indicates if the event occurred. Note that even when the
corresponding enable bit is not set in bit 7, then this bit will
still be active. It is up to the SMM code to use the enable bit
to determine the exact cause of the SMI#.
0 = Software clears this bit by writing a ’1’ to the bit location
1 = Event Occurred
Reserved.
Used to prevent the USB controller from generating an
interrupt due to transactions on its ports. When disabled, it
will be configured to generate an SMI using bit 4 of this
register. Default to ’1’ for compatibility with older USB
software.
0 = Disable
1 = Enable
Indicates if an interrupt event occurred from this controller.
The interrupt from the controller is taken before the enable in
bit 13 has any effect to create this read-only bit. Note that
even when the corresponding enable bit is not set in the Bit 4,
this bit may still be active. It is up to the SMM code to use the
enable bit to determine the exact cause of the SMI#.
0 = Software should clear the interrupts through the USB
1 = Event Occurred.
Indicates if the event occurred. Note that even when the
corresponding enable bit is not set in the bit 3, this bit will
still be active. It is up to the SMM code to use the enable bit
to determine the exact cause of the SMI#. Note that the
A20Gate Pass-Through Logic allows specific port 64h writes to
complete without setting this bit.
0 = Software clears this bit by writing a ’1’ to the bit location
1 = Event Occurred.
NOTE: If bit 7 of the ETR1 (D31:F0, offset F4h ETR1) is set.
Indicates if the event occurred. Note that even when the
corresponding enable bit is not set in the bit 2, this bit will
still be active. It is up to the SMM code to use the enable bit
to determine the exact cause of the SMI#.
0 = Software clears this bit by writing a ’1’ to the bit location
1 = Event Occurred.
NOTE: If bit 7 of the ETR1 (D31:F0, offset F4h ETR1) is set.
in any of the controllers.
controllers. Writing a ’1’ to this bit will have no effect.
in any of the controllers.
in any of the controllers.
See
Extended Features Register (LPC I/F—D31:F0)”
more information. Port 64 Writes initiated from an
external PCI agent will not set this bit.
See
Extended Features Register (LPC I/F—D31:F0)”
more information. Port 64 Reads initiated from an
external PCI agent will not set this bit.
Section 8.1.37, “Offset F4: ETR1—PCI-X
Section 8.1.37, “Offset F4: ETR1—PCI-X
Description
Attribute:
Function:
Size:
0/1
Read/Write
16-bit
Order Number: 300641-004US
Intel
for
for
®
6300ESB ICH—10
November 2007
Access
R/WC
R/WC
R/WC
R/W
RO