NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 584

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

14.1.4
Table 500. Offset 06 - 07h: PCISTA—Device Status Register (Modem—D31:F6)
Intel
DS
584
10:9
Bits
Default Value:
3:0
15
14
13
12
11
8
7
6
5
4
®
6300ESB I/O Controller Hub
Lockable:
Note: PCISTA is a 16-bit status register. Refer to the PCI 2.2 specification for complete details
Device:
DEVT (DEVSEL# Timing
Offset:
SERRS (SERR# Status)
FBC (Fast Back to back
Capabilities List Exists
STA (Signaled Target-
DPE (Detected Parity
MAS (Master-Abort
DPD (Data Parity
66 MHz Capable
UDF Supported
Abort Status)
Detected)
Offset 06 - 07h: PCISTA—Device Status Register
(Modem—D31:F6)
on each bit.
Reserved
Reserved
Capable)
(CLIST)
Status)
Status)
31
06 - 07h
0290h
No
Name
Error)
Not implemented. Hardwired to ‘0’.
Not implemented. Hardwired to ‘0’.
0 = Software clears this bit by writing a ‘1’ to the bit position.
1 = Bus Master AC ‘97 interface function, as a master,
Reserved. Read as ‘0’.
Not implemented. Hardwired to ‘0’.
This 2-bit field reflects the Intel
timing parameter. These read-only bits indicate the Intel
6300ESB ICH's DEVSEL# timing when performing a positive
decode.
Not implemented. Hardwired to ‘0’.
Hardwired to ‘1’. This bit indicates that the Intel
ICH as a target is capable of fast back-to-back transactions.
Not implemented. Hardwired to ‘0’.
Hardwired to ‘0’.
Indicates that the controller contains a capabilities pointer
list. The first item is pointed to by looking at configuration
offset 34h.
Reserved.
generates a master abort.
Power Well:
Description
Attribute:
Function:
Size:
®
6300ESB ICH's DEVSEL#
6
Read/Write Clear
16-bit
Core
®
6300ESB
Order Number: 300641-004US
Intel
®
®
6300ESB ICH—14
November 2007
Access
R/WC
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO